An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays. - Jatindra Kumar Deka; Pallab Dasgupta; P. P. Chakrabarti 001 (VLSI Design, 1999)

Model checking on timed-event structures. - Pallab Dasgupta; Jatindra Kumar Deka; Partha Pratim Chakrabarti (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Abstractions for model checking of event timings. - Jatindra Kumar Deka; S. Chaki; Pallab Dasgupta; P. P. Chakrabarti 001 (ISCAS (5), 2001)

Min-max Computation Tree Logic. - Pallab Dasgupta; P. P. Chakrabarti 001; Jatindra Kumar Deka; Sriram Sankaranarayanan 001 (Artif. Intell., 2001)

Reasoning about Extremal Properties of Events. - Jatindra Kumar Deka (TIME, 2003)

Variable Ordering of BDDs using Genetic Algorithm. - Moi Riba; Jatindra Kumar Deka (IICAI, 2005)

Fair diagnosability in PN-based DES models. - Khan Ajoy; Kushagra Misra; Santosh Biswas; Jatindra Kumar Deka; Hemangee K. Kapoor (ICCA, 2010)

Detection of faulty interswitch links in 2-D mesh network-on-chips. - Biswajit Bhowmik; Santosh Biswas; Jatindra Kumar Deka (IEEE ANTS, 2014)

Reliability on Top of Best Effort Delivery: Maximal Connectivity Test on NoC Interconnects. - Biswajit Bhowmik; Jatindra Kumar Deka; Santosh Biswas (COMPUTE, 2015)

A packet address driven test strategy for stuck-at faults in networks-on-chip interconnects. - Biswajit Bhowmik; Santosh Biswas; Jatindra Kumar Deka (MED, 2015)

An Optimal Diagnosis of NoC Interconnects on Activation of Diagonal Routers. - Biswajit Bhowmik; Santosh Biswas; Jatindra Kumar Deka (SMC, 2015)

Directed Symbolic Execution for VLSI Circuits. - Biswajit Bhowmik; Jatindra Kumar Deka; Santosh Biswas (SMC, 2015)

A Reliability-Aware Topology-Agnostic Test Scheme for Detecting, and Diagnosing Interconnect Shorts in On-chip Networks. - Biswajit Bhowmik; Santosh Biswas; Jatindra Kumar Deka (HPCC/SmartCity/DSS, 2016)

When Clustering Shows Optimality towards Analyzing Stuck-at Faults in Channels of On-chip Networks. - Biswajit Bhowmik; Jatindra Kumar Deka; Santosh Biswas (HPCC/SmartCity/DSS, 2016)

An odd-even scheme to prevent a packet from being corrupted and dropped in fault tolerant NoCs. - Biswajit Bhowmik; Santosh Biswas; Jatindra Kumar Deka (IOLTS, 2016)

An on-line test solution for addressing interconnect shorts in on-chip networks. - Biswajit Bhowmik; Jatindra Kumar Deka; Santosh Biswas (IOLTS, 2016)

Towards a Scalable Test Solution for the Analysis of Interconnect Shorts in On-chip Networks. - Biswajit Bhowmik; Jatindra Kumar Deka; Santosh Biswas (MASCOTS, 2016)

Detecting and diagnosing open faults in NoC channels on activation of diagonal nodes. - Biswajit Bhowmik; Santosh Biswas; Jatindra Kumar Deka; Bhargab B. Bhattacharya (SMC, 2016)

One poison is antidote against another poison. - Biswajit Bhowmik; Santosh Biswas; Jatindra Kumar Deka; Bhargab B. Bhattacharya (SMC, 2016)

A topology-agnostic test model for link shorts in on-chip networks. - Biswajit Bhowmik; Jatindra Kumar Deka; Santosh Biswas; Bhargab B. Bhattacharya (SMC, 2016)

On-line detection and diagnosis of stuck-at faults in channels of NoC-based systems. - Biswajit Bhowmik; Jatindra Kumar Deka; Santosh Biswas; Bhargab B. Bhattacharya (SMC, 2016)

Charka: A reliability-aware test scheme for diagnosis of channel shorts beyond mesh NoCs. - Biswajit Bhowmik; Jatindra Kumar Deka; Santosh Biswas (DATE, 2017)

A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks. - Biswajit Bhowmik; Jatindra Kumar Deka; Santosh Biswas (J. Electron. Test., 2017)

On-Line Analysis of Stuck-at Faults in On-Chip Network Interconnects. - Biswajit Bhowmik; Jatindra Kumar Deka; Santosh Biswas (J. Circuits Syst. Comput., 2018)

Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks. - Biswajit Bhowmik; Santosh Biswas; Jatindra Kumar Deka; Bhargab B. Bhattacharya (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Systematic Design of Approximate Adder Using Significance Based Gate-Level Pruning (SGLP) for Image Processing Application. - Sisir Kumar Jena; Santosh Biswas; Jatindra Kumar Deka (PReMI (2), 2019)

A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip. - Biswajit Bhowmik; Santosh Biswas; Jatindra Kumar Deka; Bhargab B. Bhattacharya (J. Electron. Test., 2019)

Test Generation for Bridging Faults in Reversible Circuits Using Path-Level Expressions. - Mousum Handique; Santosh Biswas; Jatindra Kumar Deka (J. Electron. Test., 2019)

Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip. - Biswajit Bhowmik; Jatindra Kumar Deka; Santosh Biswas; Bhargab B. Bhattacharya (ACM Trans. Design Autom. Electr. Syst., 2019)

Reliability Monitoring in a Smart NoC Component. - Biswajit Bhowmik; Jatindra Kumar Deka; Santosh Biswas (ICECS, 2020)

Locating Open-Channels in Octagon Networks on Chip-Microprocessors. - Biswajit Bhowmik; Santosh Biswas; Jatindra Kumar Deka; Bhargab B. Bhattacharya (ISVLSI, 2020)

Improving Reliability in Spidergon Network on Chip-Microprocessors. - Biswajit Bhowmik; Jatindra Kumar Deka; Santosh Biswas (MWSCAS, 2020)

Test Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels. - Biswajit Bhowmik; Santosh Biswas; Jatindra Kumar Deka (SMC, 2020)

A Fault Detection Scheme for Reversible Circuits using -Ve Control k-CNOT Based Circuit. - Mousum Handique; Jatindra Kumar Deka; Santosh Biswas (TENCON, 2020)

Maximizing Yield through Retesting of Rejected Circuits using Approximation Technique. - Sisir Kumar Jena; Santosh Biswas; Jatindra Kumar Deka (TENCON, 2020)

Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis. - Sisir Kumar Jena; Santosh Biswas; Jatindra Kumar Deka (VDAT, 2020)

An Efficient Test Set Construction Scheme for Multiple Missing-Gate Faults in Reversible Circuits. - Mousum Handique; Jatindra Kumar Deka; Santosh Biswas (J. Electron. Test., 2020)

Selective Fault-Masking for Improving Yield and Performance of On-Chip Networks. - Biswajit Bhowmik; Jatindra Kumar Deka; Santosh Biswas (SMC, 2021)

Conversion of Virtual Lab Experiments using FOSS: A Case Study of Virtual Labs by NMEICT. - Nanu Alan Kachari; Santosh Biswas; Jatindra Kumar Deka (TALE, 2021)

ATPG for Incomplete Testing of SOC Considering Bridging Faults. - Kunwer Mrityunjay Singh; Santosh Biswas; Jatindra Kumar Deka (TENCON, 2021)

Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement. - Sisir Kumar Jena; Santosh Biswas; Jatindra Kumar Deka (J. Electron. Test., 2021)

Incomplete Testing of SOC. - Kunwer Mrityunjay Singh; Jatindra Kumar Deka; Santosh Biswas (J. Electron. Test., 2023)