Application of SPICE simulation to study WDM and SCM systems using EDFAs with chirping. - Jau-Ji Jou; Cheng-Kuang Liu (IEEE Trans. Educ., 2002)

Design of pseudo-random bit sequence generator with adjustable sinusoidal jitter. - Hong-Jhih Chen; Jau-Ji Jou; Tien-Tsorng Shih (ISOCC, 2016)

High linearity transimpedance amplifier in 0.18-μm CMOS technology for 20-Gb/s PAM-4 receivers. - Chih-Chen Peng; Jau-Ji Jou; Tien-Tsorng Shih; Chien-Liang Chiu (ISOCC, 2017)

Multi-channel multi-gigabit PRBS generator with a built-in clock in 0.18-μm CMOS technology. - Chi-Hsien Wu; Jau-Ji Jou; Hsin-Wen Ting; Shao-I Chu; Bing-Hong Liu (ISOCC, 2017)

Few-mode 850-nm VCSEL chip with direct 16-QAM OFDM encoding at 80-Gbit/s for 100-m OM4 MMF link. - Hsuan-Yun Kao; Cheng-Ting Tsai; Chun-Yen Pong; Shan-Fong Liang; Zu-Kai Weng; Yu-Chieh Chi; Hao-Chung Kuo; Jian Jang Huang; Tai-Cheng Lee; Tien-Tsorng Shih; Jau-Ji Jou; Wood-Hi Cheng; et al. (OFC, 2017)

25 Gb/s NRZ and 50 Gb/s PAM-4 Transimpedance Amplifier with Active Feedback and Equalization in 90 nm CMOS Technology. - Hao-Wen Hsu; Chih-Chen Peng; Jau-Ji Jou; Tien-Tsorng Shih; Yaw-Dung Wu; Shao-I Chu; Chih-Yuan Lien; Bing-Hong Liu (ICETE (1), 2019)

Design of High-Speed Optical Receiver Module for 160Gb/s NRZ and 200Gb/s PAM4 Transmissions. - Jian-Yu Lai; Chuan-Yu Liao; Jau-Ji Jou; Tien-Tsorng Shih; Po-Jui Chiang (ISCAS, 2019)

Design of a 25-Gb/s PAM-4 VCSEL Diode Driver with an Equalizer in 90-nm CMOS Technology. - Tsung-Yen Wu; Jau-Ji Jou; Tien-Tsorng Shih; Po-Jui Chiang; Yaw-Dung Wu (ISCAS, 2019)

A 40-Gb/s NRZ Inductorless Transimpedance Amplifier in a 0.18-μm SiGe BiCMOS Technology. - Hao-Wen Hsu; Xuan-Yi Ye; Jau-Ji Jou; Tien-Tsorng Shih (ISPACS, 2021)

Performance Monitoring of High-Speed NRZ Signals Using Machine Learning Techniques. - Chun-Chen Yao; Jun-Yuan Zheng; Jau-Ji Jou; Chun-Liang Yang (ISPACS, 2021)

The Study of 60 GHz Wideband Conductor-Backed Coplanar Waveguide on a TGV Substrate. - C. L. Chiu; Ting-Rong Chen; Chia-Wei Lee; Jau-Ji Jou (GCCE, 2022)

An Algorithm Design for Minimum-Latency Scheduling in Multiple-Data-Type Multi-Channel WSNs. - Vinh V. Le; Dung H. P. Nguyen; Bing-Hong Liu; Shao-I Chu; Chih-Yuan Lien; Jau-Ji Jou (GCCE, 2022)

32-Gb/s NRZ and 40-Gb/s PAM-4 Transimpedance Amplifier Paralleling with a Differentiator for Bandwidth Enhancement in 90-nm CMOS Technology. - Jau-Ji Jou; Tien-Tsorng Shih; Hao-Wen Hsu (Circuits Syst. Signal Process., 2022)

The Abnormal Events Detection System by Feature Enhancement-Based Deep Learning Network. - Chao-Ho Chen; Tsong-Yi Chen; Yong-Lin Chen; Bing-Hong Liu; Jau-Ji Jou; Cheng-Kang Wen (GCCE, 2023)