Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. - Rosa Rodríguez-Montañés; Jaume A. Segura 001; Víctor H. Champac; Joan Figueras; J. A. Rubio (ITC, 1991)

Quiescent current analysis and experimentation of defective CMOS circuits. - Jaume A. Segura 001; Víctor H. Champac; Rosa Rodríguez-Montañés; Joan Figueras; J. A. Rubio (J. Electron. Test., 1992)

A built-in quiescent current monitor for CMOS VLSI circuits. - Antonio Rubio 001; Edmond Janssens; H. Casier; Joan Figueras; Diego Mateo; P. De Pauw; Jaume Segura 001 (ED&TC, 1995)

A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level. - Jaume Segura 001; Carol de Benito; Antonio Rubio 001; Charles F. Hawkins (ITC, 1995)

An approach to dynamic power consumption current testing of CMOS ICs. - Jaume A. Segura 001; Miquel Roca 001; Diego Mateo; Antonio Rubio 001 (VTS, 1995)

A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors. - Jaume Segura 001; Carol de Benito; Antonio Rubio 001; Charles F. Hawkins (J. Electron. Test., 1996)

A detailed analysis of CMOS SRAM's with gate oxide short defects. - Jaume Segura 001; Antonio Rubio 001 (IEEE J. Solid State Circuits, 1997)

Integrated Cmos Linear Dosimeter. - Oscar Calvo; M. González; C. Romero; Eugenio García-Moreno; Eugeni Isern 001; Miquel Roca 001; Jaume Segura 001 (SBCCI, 1998)

Clocked Dosimeter Compatible with Digital CMOS Technology. - Eugenio García-Moreno; Benjamín Iñíguez; Miquel Roca 001; Jaume Segura 001; Eugeni Isern 001 (J. Electron. Test., 1998)

A variable threshold voltage inverter for CMOS programmable logic circuits. - Jaume Segura 001; José Luis Rosselló; J. Morra; H. Sigg (IEEE J. Solid State Circuits, 1998)

Analyzing the Need for ATPG Targeting GOS Defects. - Eugeni Isern 001; Miquel Roca 001; Jaume Segura 001 (VTS, 1999)

Test and Reliability: Partners in IC Manufacturing, Part 1. - Charles F. Hawkins; Jaume Segura 001 (IEEE Des. Test Comput., 1999)

Test and Reliability: Partners in IC Manufacturing, Part 2. - Charles F. Hawkins; Jaume Segura 001; Jerry M. Soden; Ted Dellin (IEEE Des. Test Comput., 1999)

On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor. - Bartomeu Alorda; Ivan de Paúl; Jaume Segura 001; T. Miller (IOLTW, 2000)

Transient Current Monitoring Using a Current-to-Frequency Converter. - Rodrigo Picos; J. Colom; Miquel Roca 001; Eugeni Isern 001; Jaume Segura 001; Oscar Calvo; Eugenio García-Moreno (LATW, 2000)

Experimental Results on BIC Sensors for Transient Current Testing. - Rodrigo Picos; Miquel Roca 001; Eugeni Isern 001; Jaume Segura 001; Eugenio García-Moreno (J. Electron. Test., 2000)

Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. - José Luis Rosselló; Jaume Segura 001 (ICCAD, 2001)

Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments. - Ivan de Paúl; M. Rosales; Bartomeu Alorda; Jaume Segura 001; Charles F. Hawkins; Jerry M. Soden (VTS, 2001)

A novel wavelet transform based transient current analysis for fault detection and localization. - Swarup Bhunia; Kaushik Roy 001; Jaume Segura 001 (DAC, 2002)

An Off-Chip Sensor Circuit for On-Line Transient Current Testing. - Bartomeu Alorda; André Ivanov; Jaume Segura 001 (IOLTW, 2002)

A BICS for CMOS Opamps by Monitoring the Supply Current Peak. - Joan Font; J. Ginard; Eugeni Isern 001; Miquel Roca 001; Jaume Segura 001; Eugenio García (IOLTW, 2002)

Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs. - Bartomeu Alorda; M. Rosales; Jerry M. Soden; Charles F. Hawkins; Jaume Segura 001 (ITC, 2002)

GHz Testing and Its Fuzzy Targets. - Chuck Hawkins; Jaume Segura 001 (ITC, 2002)

Parametric Failures in CMOS ICs - A Defect-Based Analysis. - Jaume Segura 001; Ali Keshavarzi; Jerry M. Soden; Charles F. Hawkins (ITC, 2002)

A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers. - José Luis Rosselló; Jaume Segura 001 (PATMOS, 2002)

Challenges in Nanometric Technology Scaling: Trends and Projections. - Jaume Segura 001; Vivek De; Ali Keshavarzi (VTS, 2002)

Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era. - Jaume Segura 001; Peter C. Maxwell (IEEE Des. Test Comput., 2002)

Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers. - José Luis Rosselló; Jaume Segura 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

CMOS IC nanometer technology failure mechanisms. - Charles F. Hawkins; Ali Keshavarzi; Jaume Segura 001 (CICC, 2003)

A View from the Bottom: Nanometer Technology AC Parametric Failures – Why, Where, and How to Detect. - Charles F. Hawkins; Ali Keshavarzi; Jaume Segura 001 (DFT, 2003)

An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing. - Bartomeu Alorda; Jaume Segura 001 (IOLTS, 2003)

CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing. - Bartomeu Alorda; Brad Bloechel; Ali Keshavarzi; Jaume Segura 001 (ITC, 2003)

A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates. - José Luis Rosselló; Jaume Segura 001 (PATMOS, 2003)

Structural RFIC device testing through built-in thermal monitoring. - Josep Altet; Antonio J. Rubio; José Luis Rosselló; Jaume Segura 001 (IEEE Commun. Mag., 2003)

A BICS for CMOS OpAmps by Monitoring the Supply Current Peak. - Joan Font; J. Ginard; Rodrigo Picos; Eugeni Isern 001; Jaume Segura 001; Miquel Roca 001; Eugenio García (J. Electron. Test., 2003)

A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. - José Luis Rosselló; Jaume Segura 001 (DATE, 2004)

A BIST-based Charge Analysis for Embedded Memories. - Bartomeu Alorda; Vicent Canals; Ivan de Paúl; Jaume Segura 001 (IOLTS, 2004)

Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. - Sebastià A. Bota; M. Rosales; José Luis Rosselló; Jaume Segura 001; Ali Keshavarzi (ITC, 2004)

A Two-Level Power-Grid Model for Transient Current Testing Evaluation. - Bartomeu Alorda; Vincent Canals; Jaume Segura 001 (J. Electron. Test., 2004)

An analytical charge-based compact delay model for submicrometer CMOS inverters. - José Luis Rosselló; Jaume A. Segura 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. - Sebastià A. Bota; M. Rosales; José Luis Rosselló; Jaume Segura 001 (DATE, 2005)

A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. - José Luis Rosselló; Vicent Canals; Sebastià A. Bota; Ali Keshavarzi; Jaume Segura 001 (DATE, 2005)

The anatomy of nanometer timing failures. - Chuck Hawkins; Jaume Segura 001 (ETS, 2005)

A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits. - Bartomeu Alorda; Sebastià A. Bota; Jaume Segura 001 (IOLTS, 2005)

Compact Static Power Model of Complex CMOS Gates. - José Luis Rosselló; Sebastià A. Bota; Jaume Segura 001 (PATMOS, 2005)

A compact gate-level energy and delay model of dynamic CMOS gates. - José Luis Rosselló; Carol de Benito; Jaume Segura 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

A compact model to identify delay faults due to crosstalk. - José Luis Rosselló; Jaume Segura 001 (DATE, 2006)

CMOS Testing at the End of the Roadmap: Challenges and Opportunities. - Jaume Segura 001 (DDECS, 2006)

A Fully CMOS Low-Cost Chaotic Neural Network. - José Luis Rosselló; Sebastià A. Bota; Vicent Canals; Ivan de Paúl; Jaume Segura 001 (IJCNN, 2006)

Leakage Power Characterization Considering Process Variations. - José Luis Rosselló; Carol de Benito; Sebastià A. Bota; Jaume Segura 001 (PATMOS, 2006)

Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. - Sebastià A. Bota; M. Rosales; José Luis Rosselló; Jaume Segura 001 (VTS, 2006)

Impact of Thermal Gradients on Clock Skew and Testing. - Sebastià A. Bota; José Luis Rosselló; Carol de Benito; Ali Keshavarzi; Jaume Segura 001 (IEEE Des. Test Comput., 2006)

Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. - José Luis Rosselló; Carol de Benito; Sebastià A. Bota; Jaume Segura 001 (DATE, 2007)

Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment. - X. Cano; Sebastià A. Bota; Ricardo Graciani Diaz; David Gascon; A. Herms; Albert Comerma; Jaume Segura 001; Lluís Garrido (IOLTS, 2007)

Charge-based testing BIST for embedded memories. - Bartomeu Alorda; Ivan de Paúl; Jaume Segura 001 (IET Comput. Digit. Tech., 2007)

Using stochastic logic for efficient pattern recognition analysis. - José Luis Rosselló; Vincent Canals; Ivan de Paúl; Jaume Segura 001 (IJCNN, 2008)

A modern look at the CMOS stuck-open fault. - Roberto Gómez 001; Víctor H. Champac; Chuck Hawkins; Jaume Segura 001 (LATW, 2009)

Stuck-Open Fault Leakage and Testing in Nanometer Technologies. - Julio César Vázquez; Víctor H. Champac; Chuck Hawkins; Jaume Segura 001 (VTS, 2009)

Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs. - Bartomeu Alorda; Gabriel Torrens; Sebastià A. Bota; Jaume Segura 001 (DATE, 2010)

Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories. - Sebastià A. Bota; Gabriel Torrens; Bartomeu Alorda; Jaume Verd; Jaume Segura 001 (IOLTS, 2010)

Reliability analysis of small delay defects in vias located in signal paths. - Hector Villacorta; Víctor H. Champac; Chuck Hawkins; Jaume Segura 001 (LATW, 2010)

Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination. - Gabriel Torrens; Bartomeu Alorda; Salvador Barceló; José Luis Rosselló; Sebastià A. Bota; Jaume Segura 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation. - Bartomeu Alorda; Gabriel Torrens; Sebastià A. Bota; Jaume Segura 001 (DATE, 2011)

An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation. - Salvador Barceló; Xavier Gili; Sebastià A. Bota; Jaume Segura 001 (DATE, 2011)

8T vs. 6T SRAM cell radiation robustness: A comparative analysis. - Bartomeu Alorda; Gabriel Torrens; Sebastià A. Bota; Jaume Segura 001 (Microelectron. Reliab., 2011)

Testing of Stuck-Open Faults in Nanometer Technologies. - Víctor H. Champac; Julio Vazquez Hernandez; Salvador Barceló; Roberto Gómez 001; Chuck Hawkins; Jaume Segura 001 (IEEE Des. Test Comput., 2012)

Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test. - Hector Villacorta; Víctor H. Champac; Sebastià A. Bota; Jaume Segura 001 (Microelectron. Reliab., 2012)

Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias. - Hector Villacorta; Jose Luis Garcia-Gervacio; Víctor H. Champac; Sebastià A. Bota; Jaime Martínez-Castillo; Jaume Segura 001 (LATW, 2013)

Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths. - Hector Villacorta; Charles F. Hawkins; Víctor H. Champac; Jaume Segura 001; Roberto Gómez 001 (IEEE Des. Test, 2013)

Alternate characterization technique for static random-access memory static noise margin determination. - José Luis Merino; Sebastià Antoni Bota; Rodrigo Picos; Jaume Segura 001 (Int. J. Circuit Theory Appl., 2013)

Analysis of fin height on FinFET SRAM cell hardening. - Hector Villacorta; Jaume Segura 001; Sebastià A. Bota; Víctor H. Champac (MWSCAS, 2014)

Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells. - Bartomeu Alorda; Gabriel Torrens; Sebastià A. Bota; Jaume Segura 001 (Microelectron. Reliab., 2014)

Sensitization Input Vector Impact on Propagation Delay for Nanometer CMOS ICs: Analysis and Solutions. - Salvador Barceló; Xavier Gili; Sebastià A. Bota; Jaume Segura 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell. - Hector Villacorta; Roberto Gómez 001; Sebastià A. Bota; Jaume Segura 001; Víctor H. Champac (LATS, 2015)

Low VDD and body bias conditions for testing bridge defects in the presence of process variations. - Hector Villacorta; Jose Luis Garcia-Gervacio; Jaume Segura 001; Víctor H. Champac (Microelectron. J., 2015)

Electrostatically actuated microbeam resonators as chaotic signal generators: A practical perspective. - Joan Barceló; José Luis Rosselló; Sebastià A. Bota; Jaume Segura 001; Jaume Verd (Commun. Nonlinear Sci. Numer. Simul., 2016)

Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability. - Hector Villacorta; Jaume Segura 001; Víctor H. Champac (J. Electron. Test., 2016)

Cantilever NEMS relay-based SRAM devices for enhanced reliability. - Sebastià A. Bota; Jaume Verd; Joan Barceló; Xavier Gili; Bartomeu Alorda; Gabriel Torrens; Carol de Benito; Jaume Segura 001 (DTIS, 2017)

Integrated microelectromechanical systems in the More than Moore era. - Jaume Segura 001 (DTIS, 2017)

Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells. - Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Gabriel Torrens; Sebastià A. Bota; Jaume Segura 001; Francesc Moll; Antonio Rubio 001 (SMACD, 2017)

Soft error rate comparison of 6T and 8T SRAM ICs using mono-energetic proton and neutron irradiation sources. - Daniel Malagón; Sebastià A. Bota; Gabriel Torrens; Xavier Gili; Javier Praena; B. Fernández; Miguel Macías; José Manuel Quesada 001; Carlos Guerrero Sanchez; María del Carmen Jiménez-Ramos; Javier García López; José Luis Merino; et al. (Microelectron. Reliab., 2017)

Bistability in a CMOS-MEMS Thermally Tuned Microbeam Resonator. - Joan Barceló; Ivan de Paúl; Sebastià A. Bota; Jaume Segura 001; Jaume Verd (ISCAS, 2018)

Frequency Fluctuations in CMOS-MEMS Oscillators: Towards the Thermomechanical Limit. - Rafel Perelló-Roig; Jaume Verd; Sebastià A. Bota; Jaume Segura 001 (ISCAS, 2018)

Thermomechanical Noise Characterization in Fully Monolithic CMOS-MEMS Resonators. - Rafel Perelló-Roig; Jaume Verd; Sebastià A. Bota; Jaume Segura 001 (Sensors, 2018)

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors. - Gabriel Torrens; Bartomeu Alorda; Cristian Carmona; Daniel Malagón-Periánez; Jaume Segura 001; Sebastià A. Bota (IEEE Trans. Emerg. Top. Comput., 2019)

Impact of Fluid Flow on CMOS-MEMS Resonators Oriented to Gas Sensing. - Rafel Perelló-Roig; Jaume Verd; Sebastià A. Bota; Jaume Segura 001 (Sensors, 2020)

Fully Integrated Front-End CMOS-MEMS Transducer for Low-Cost Real-Time Breath Monitoring. - Rafel Perelló-Roig; Francisca Orvay; Ivan de Paúl; Jaume Verd; Sebastià A. Bota; Jaume Segura 001 (IEEE SENSORS, 2022)

A Compact Double-Exponential Circuit for Single Event Transient Emulation. - Sebastià A. Bota; Salvador Barceló; Gabriel Torrens; Rafel Perelló; Jaume Verd; Ivan de Paúl; Jaume Segura 001 (DCIS, 2023)

Design Guidelines for β-Multiplier Current Reference Circuits. - Sebastià A. Bota; Rafel Perelló; Salvador Barceló; Ivan de Paúl; Jaume Segura 001; Jaume Verd (DCIS, 2024)

A 164-dBΩ Transimpedance Amplifier for Monolithic CMOS-MEMS Oscillators in Biosensing Applications. - Rafel Perelló-Roig; Salvador Barceló; Jaume Verd; Sebastià A. Bota; Jaume Segura 001 (IEEE Access, 2024)

SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results. - Gabriel Torrens; Ivan de Paúl; Bartomeu Alorda; Sebastià A. Bota; Jaume Segura 001 (CoRR, 2024)

Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment. - Daniel Malagón; Gabriel Torrens; Jaume Segura 001; Sebastià A. Bota (CoRR, 2024)

Failure Probability due to Radiation-Induced Effects in FinFET SRAM Cells under Process Variations. - Víctor H. Champac; Hector Villacorta; Roberto Gómez-Fuentes; Fabian Vargas 001; Jaume Segura 001 (J. Electron. Test., 2024)