An Architectural Level Test Generator for a Hierarchical Design Environment. - Jaushin Lee; Janak H. Patel (FTCS, 1991)

A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation. - Jaushin Lee; Janak H. Patel (ICCAD, 1991)

ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults. - Jaushin Lee; Janak H. Patel (ITC, 1991)

Hierarchical Test Generation under Intensive Global Functional Constraints. - Jaushin Lee; Janak H. Patel (DAC, 1992)

A comparative study of design for testability methods using high-level and gate-level descriptions. - Vivek Chickermane; Jaushin Lee; Janak H. Patel (ICCAD, 1992)

Design for Testability Using Architectural Descriptions. - Vivek Chickermane; Jaushin Lee; Janak H. Patel (ITC, 1992)

An Instruction Sequence Assembling Methodology for Testing Microprocessors. - Jaushin Lee; Janak H. Patel (ITC, 1992)

Architectural Level Test Generation and Fault Simulation - Jaushin Lee (1992)

Impact of high level functional constraints on testability. - Jaushin Lee; Vivek Chickermane; Janak H. Patel (VTS, 1993)

Testability analysis based on structural and behavioral information. - Jaushin Lee; Janak H. Patel (VTS, 1993)

An architectural level test generator based on nonlinear equation solving. - Jaushin Lee; Janak H. Patel (J. Electron. Test., 1993)

Addressing design for testability at the architectural level. - Vivek Chickermane; Jaushin Lee; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Architectural level test generation for microprocessors. - Jaushin Lee; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Hierarchical test generation under architectural level functional constraints. - Jaushin Lee; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)