Soft error analysis of MTJ-based logic-in-memory full adder: Threats and solution. - Javad Talafy; Hamid R. Zarandi (IOLTS, 2017)

DUSTER: DUal Source Write TERmination Method for STT-RAM Memories. - Saaed S. Faraji; Javad Talafy; Amir M. Hajisadeghi; Hamid R. Zarandi (DSD, 2018)

DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories. - Saeed Seyedfaraji; Amir M. Hajisadeghi; Javad Talafy; Hamid R. Zarandi (Microprocess. Microsystems, 2020)

A High Performance, Multi-Bit Output Logic-in-Memory Adder. - Javad Talafy; Farzaneh Zokaee; Hamid R. Zarandi; Nader Bagherzadeh (IEEE Trans. Emerg. Top. Comput., 2021)

EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit. - Saeed Seyedfaraji; Javad Talafy; Mohamed M. Sabry; Semeen Rehman (CoRR, 2022)