Novel spike-based architecture for RFID and Sensor communication system. - Manjunath Machnoor; Javed S. Gaggatur; K. Sanjeev (IECON, 2015)

A 3.2 mW 0.13 μm high sensitivity frequency-domain CMOS capacitance interface. - Javed S. Gaggatur; Pradeep K. Dixena; Gaurab Banerjee (ISCAS, 2016)

Noise analysis in ring oscillator-based capacitance sensor interface. - Javed S. Gaggatur; Gaurab Banerjee (MWSCAS, 2016)

A 13.5 bit 1.6 mW 3rd order CT ΣΔ ADC for integrated capacitance sensor interface. - Javed S. Gaggatur; Gaurab Banerjee (SoCC, 2017)

High Gain Capacitance Sensor Interface for the Monitoring of Cell Volume Growth. - Javed S. Gaggatur; Gaurab Banerjee (VLSID, 2017)

On-Chip Non-intrusive Temperature Detection and Compensation of a Fully Integrated CMOS RF Power Amplifier. - Javed S. Gaggatur; Immanuel Raja; Gaurab Banerjee (VLSID, 2017)

A 1.25-20 GHz Wide Tuning Range Frequency Synthesis for 40-Gb/s SerDes Application. - Javed S. Gaggatur; Abhishek Chaturvedi (VDAT, 2019)

A 75-µW 2.4 GHz Wake-up Receiver in 65-nm CMOS for Neonatal Healthcare Application. - Kundan Kumar; Raghunath K. P; Akshay Muraleedharan; Javed S. Gaggatur; Gaurab Banerjee (VLSID, 2019)

A tunable, power efficient active inductor-based 20 Gb/s CTLE in SerDes for 5G applications. - Deepanraj Thulasiraman; Javed S. Gaggatur (Microelectron. J., 2020)

A 1.8 - 6.3 GHz Quadrature Ring VCO-based Fast-settling PLL for Wireline I/O in 55nm CMOS. - Javed S. Gaggatur (VLSID, 2021)

A 0.6 V, 2nd order low-pass Gm-C filter using CMOS inverter-based tunable OTA with 1.114 GHz cut-off frequency in 90nm CMOS technology. - Nisarga Ramesh; Javed S. Gaggatur (VLSID, 2021)

A Duty Cycle Error Reduction with 1-point Calibration achieving 0.017UI in 7.2Gbps HBM3 DRAM Data Read. - Javed S. Gaggatur (SOCC, 2022)

Noise Analysis of CMOS Ring Oscillator-based Capacitance Measurement for Lab-on-Chip Application. - Javed S. Gaggatur (SOCC, 2022)

A 0.009mm2, 0-230mA Wide-range Load Current Output Capacitor-less Low Dropout Regulator for High Bandwidth Memory parallel IOs. - Javed S. Gaggatur; Miryala Chandra Shekar; Komal Deshmukh (VLSID, 2022)

A 0.5pJ/bit 7.2Gbps HBM3 PHY on Intel4 with EMIB Packaging and Unmatched Receiver Architecture on PHY Side with Per Bit Deskew Correction. - Aakash Hasmukhray Mehta; Javed S. Gaggatur; Mohammad M. Rashid; Sampath Dakshinamurthy; Aruna Kumar Lakya Srinivasamurthy; Anil Kumar Goyal; Subbarao Manam; Harshit Gupta; Sandeep Sukumar; Vipin K. Mishra; Koushik N. S; Santosh Nekkanti; et al. (VLSID, 2025)