Immediate mode scheduling in grid systems. - Fatos Xhafa; Javier Carretero; Leonard Barolli; Arjan Durresi (Int. J. Web Grid Serv., 2007)

Requirements for an Event-Based Simulation Package for Grid Systems. - Fatos Xhafa; Javier Carretero; Leonard Barolli; Arjan Durresi (J. Interconnect. Networks, 2007)

Issue system protection mechanisms. - Pedro Chaparro; Jaume Abella 001; Javier Carretero; Xavier Vera (ICCD, 2008)

On-Line Failure Detection and Confinement in Caches. - Jaume Abella 001; Pedro Chaparro; Xavier Vera; Javier Carretero; Antonio González 001 (IOLTS, 2008)

Design and evaluation of tabu search method for job scheduling in distributed environments. - Fatos Xhafa; Javier Carretero; Enrique Alba 001; Bernabé Dorronsoro (IPDPS, 2008)

On-line Failure Detection in Memory Order Buffers. - Javier Carretero; Xavier Vera; Pedro Chaparro; Jaume Abella 001 (ITC, 2008)

Online error detection and correction of erratic bits in register files. - Xavier Vera; Jaume Abella 001; Javier Carretero; Pedro Chaparro; Antonio González 001 (IOLTS, 2009)

End-to-end register data-flow continuous self-test. - Javier Carretero; Pedro Chaparro; Xavier Vera; Jaume Abella 001; Antonio González 001 (ISCA, 2009)

Low Vccmin fault-tolerant cache with highly predictable performance. - Jaume Abella 001; Javier Carretero; Pedro Chaparro; Xavier Vera; Antonio González 001 (MICRO, 2009)

A Tabu Search Algorithm for Scheduling Independent Jobs in Computational Grids. - Fatos Xhafa; Javier Carretero; Bernabé Dorronsoro; Enrique Alba 001 (Comput. Informatics, 2009)

Selective replication: A lightweight technique for soft errors. - Xavier Vera; Jaume Abella 001; Javier Carretero; Antonio González 001 (ACM Trans. Comput. Syst., 2009)

The split register file. - Jaume Abella 001; Javier Carretero; Pedro Chaparro; Xavier Vera (DATE, 2010)

High-Performance low-vcc in-order core. - Jaume Abella 001; Pedro Chaparro; Xavier Vera; Javier Carretero; Antonio González 001 (HPCA, 2010)

Microarchitectural Online Testing for Failure Detection in Memory Order Buffers. - Javier Carretero; Xavier Vera; Pedro Chaparro; Jaume Abella 001 (IEEE Trans. Computers, 2010)

Control-Flow Recovery Validation Using Microarchitectural Invariants. - Javier Carretero; Jaume Abella 001; Xavier Vera; Pedro Chaparro (DFT, 2011)

Hardware/software-based diagnosis of load-store queues using expandable activity logs. - Javier Carretero; Xavier Vera; Jaume Abella 001; Tanausú Ramírez; Matteo Monchiero; Antonio González 001 (HPCA, 2011)

Implementing End-to-End Register Data-Flow Continuous Self-Test. - Javier Carretero; Pedro Chaparro; Xavier Vera; Jaume Abella 001; Antonio González 001 (IEEE Trans. Computers, 2011)

Capturing vulnerability variations for register files. - Javier Carretero; Enric Herrero; Matteo Monchiero; Tanausú Ramírez; Xavier Vera (DATE, 2013)

Low-cost and efficient fault detection and diagnosis schemes for modern cores. - Javier Sebastian Carretero Casado (2015)