Optimization of Master-Slave Flip-Flops for High-Performance Applications. - Raúl Jiménez; Pilar Parra Fernández; Javier Castro-Ramirez; Manuel Sanchez-Raya; Antonio J. Acosta 001 (PATMOS, 2006)

A switching noise vision of the optimization techniques for low-power synthesis. - Javier Castro-Ramirez; Pilar Parra Fernández; Manuel Valencia-Barrero; Antonio J. Acosta 001 (ECCTD, 2007)

Asymmetric clock driver for improved power and noise performances. - Javier Castro-Ramirez; Pilar Parra Fernández; Manuel Valencia-Barrero; Antonio J. Acosta 001 (ISCAS, 2007)

Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. - Javier Castro-Ramirez; Pilar Parra Fernández; Antonio J. Acosta 001 (PATMOS, 2009)

Optimization of clock-gating structures for low-leakage high-performance applications. - Javier Castro-Ramirez; Pilar Parra Fernández; Antonio J. Acosta 001 (ISCAS, 2010)

Reducing bit flipping problems in SRAM physical unclonable functions for chip identification. - Susana Eiroa; Javier Castro-Ramirez; Macarena Cristina Martínez-Rodríguez; Erica Tena; Piedad Brox; Iluminada Baturone (ICECS, 2012)

ASIC-in-the-loop methodology for verification of piecewise affine controllers. - Macarena C. Martínez-Rodríguez; Piedad Brox; Javier Castro-Ramirez; Erica Tena; Antonio J. Acosta 001; Iluminada Baturone (ICECS, 2012)

A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions. - Piedad Brox; Javier Castro-Ramirez; Macarena C. Martínez-Rodríguez; Erica Tena; Carlos Jesús Jiménez-Fernández; Iluminada Baturone; Antonio J. Acosta 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Low-Power Differential Logic Gates for DPA Resistant Circuits. - Erica Tena-Sánchez; Javier Castro-Ramirez; Antonio J. Acosta 001 (DSD, 2014)

Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications. - Erica Tena-Sánchez; Javier Castro-Ramirez; Antonio J. Acosta 001 (PATMOS, 2014)

A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits. - Erica Tena-Sánchez; Javier Castro-Ramirez; Antonio J. Acosta 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)