A parallel markovian model reliability algorithm for hypercube networks. - Emilio L. Zapata; Javier D. Bruguera; Oscar G. Plata; Francisco F. Rivera (Microprocessing and Microprogramming, 1989)

ACLE: A Software Package for SIMD Computer Simulation. - Oscar G. Plata; Javier D. Bruguera; Francisco F. Rivera; Ramon Doallo; Emilio L. Zapata (Comput. J., 1990)

A reliability model for multiprocessor networks with degradable nodes. - Javier D. Bruguera; Emilio L. Zapata; Oscar G. Plata (Microprocessing and Microprogramming, 1990)

Multidimensional fast Hartley transform onto SIMD hypercubes. - Emilio L. Zapata; Francisco Argüello; Francisco Fernandez Rivera; Javier D. Bruguera (Microprocessing and Microprogramming, 1990)

Parallel quadrant interlocking factorization on hypercube computers. - Inmaculada García; Juan Julián Merelo Guervós; Javier D. Bruguera; Emilio L. Zapata (Parallel Comput., 1990)

Gaussian elimination with pivoting on hypercubes. - Francisco F. Rivera; Ramon Doallo; Javier D. Bruguera; Emilio L. Zapata; Richard L. Peskin (Parallel Comput., 1990)

Design of a constant geometry fast Hartley transformer. - Francisco Argüello; Ramon Doallo; Javier D. Bruguera; Emilio L. Zapata (ICASSP, 1991)

Image reconstruction on hypercube computers: Application to electron microscopy. - Emilio L. Zapata; Ignacio Benavides; Francisco F. Rivera; Javier D. Bruguera; Tomás F. Pena; José María Carazo (Signal Process., 1992)

Design of a Pipelined Radix 4 CORDIC Processor. - Javier D. Bruguera; Elisardo Antelo; Emilio L. Zapata (Parallel Comput., 1993)

Parallel Architecture for Fast Transforms with Trigonometric Kernel. - Francisco Argüello; Javier D. Bruguera; Ramon Doallo; Emilio L. Zapata (IEEE Trans. Parallel Distributed Syst., 1994)

Redundant CORDIC Rotator Based on Parallel Prediction. - Elisardo Antelo; Javier D. Bruguera; Julio Villalba; Emilio L. Zapata (IEEE Symposium on Computer Arithmetic, 1995)

Digit On-line Large Radix CORDIC Rotator. - Roberto R. Osorio; Elisardo Antelo; Javier D. Bruguera; Julio Villalba; Emilio L. Zapata (ASAP, 1995)

CORDIC Architectures with Parallel Compensation of the Scale Factor. - Julio Villalba; José Antonio Hidalgo López; Emilio L. Zapata; Elisardo Antelo; Javier D. Bruguera (ASAP, 1995)

2-D DCT using on-line arithmetic. - Javier D. Bruguera; Tomás Lang (ICASSP, 1995)

A Parallel Architecture for the Self-Sorting FFT Algorithm. - Francisco Argüello; Javier D. Bruguera; Emilio L. Zapata (J. Parallel Distributed Comput., 1995)

High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining. - Montserrat Bóo; Francisco Argüello; Javier D. Bruguera; Emilio L. Zapata (ASAP, 1996)

Radix-4 Vectoring Cordic Algorithm And Architectures. - Julio Villalba; J. C. Arrabal; Emilio L. Zapata; Elisardo Antelo; Javier D. Bruguera (ASAP, 1996)

High Radix Cordic Rotation Based on Selection by Rounding. - Elisardo Antelo; Javier D. Bruguera; Tomás Lang; Julio Villalba; Emilio L. Zapata (Euro-Par, Vol. II, 1996)

High performance VLSI architecture for the trellis coded quantization. - Montserrat Bóo; Francisco Argüello; Javier D. Bruguera; Emilio L. Zapata (ICIP (2), 1996)

Unified Mixed Radix 2-4 Redundant CORDIC Processor. - Elisardo Antelo; Javier D. Bruguera; Emilio L. Zapata (IEEE Trans. Computers, 1996)

Cordic based parallel/pipelined architecture for the Hough transform. - Javier D. Bruguera; Nicolás Guil; Tomás Lang; Julio Villalba; Emilio L. Zapata (J. VLSI Signal Process., 1996)

New arithmetic coder/decoder architectures based on pipelining. - Roberto R. Osorio; Javier D. Bruguera (ASAP, 1997)

A VLSI implementation of an arithmetic coder for image compression. - Mercedes Peón; Roberto R. Osorio; Javier D. Bruguera (EUROMICRO, 1997)

VLSI implementation of an area-efficient architecture for the Viterbi algorithm. - Carlos Cabrera; Montserrat Bóo; Javier D. Bruguera (ICASSP, 1997)

Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm. - Elisardo Antelo; Javier D. Bruguera; Tomás Lang; Emilio L. Zapata (IEEE Trans. Computers, 1997)

High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. - Elisardo Antelo; Julio Villalba; Javier D. Bruguera; Emilio L. Zapata (IEEE Trans. Computers, 1997)

High-performance VLSI architecture for the Viterbi algorithm. - Montserrat Bóo; Francisco Argüello; Javier D. Bruguera; Ramon Doallo; Emilio L. Zapata (IEEE Trans. Commun., 1997)

Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures. - Montserrat Bóo; Francisco Argüello; Javier D. Bruguera; Emilio L. Zapata (J. VLSI Signal Process., 1997)

Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory. - Roberto R. Osorio; Montserrat Bóo; Javier D. Bruguera (EUROMICRO, 1998)

Leading-one prediction scheme for latency improvement in single datapath floating-point adders. - Javier D. Bruguera; Tomás Lang (ICCD, 1998)

Computation of sqrt(x/d) in a Very High Radix Combined Division/Square-Root Unit with Scaling. - Elisardo Antelo; Tomás Lang; Javier D. Bruguera (IEEE Trans. Computers, 1998)

A novel design of a two operand normalization circuit. - Elisardo Antelo; Montserrat Bóo; Javier D. Bruguera; Emilio L. Zapata (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Radix-4 Vectoring CORDIC Algorithm and Architectures. - Julio Villalba; Emilio L. Zapata; Elisardo Antelo; Javier D. Bruguera (J. VLSI Signal Process., 1998)

Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. - Elisardo Antelo; Tomás Lang; Javier D. Bruguera (IEEE Symposium on Computer Arithmetic, 1999)

Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition. - Tomás Lang; Javier D. Bruguera (ICCD, 1999)

New model for arithmetic coding/decoding of multilevel images based on a cache memory. - Roberto R. Osorio; Javier D. Bruguera (ICECS, 1999)

Leading-One Prediction with Concurrent Position Correction. - Javier D. Bruguera; Tomás Lang (IEEE Trans. Computers, 1999)

Parallel Architecture for Conversion of NURBS Curves to Bézier Curves. - Paula N. Mallón; Montserrat Bóo; Javier D. Bruguera (EUROMICRO, 2000)

Architectures for arithmetic coding in image compression. - Roberto R. Osorio; Javier D. Bruguera (EUSIPCO, 2000)

Multilevel Reverse-Carry Adder. - Javier D. Bruguera; Tomás Lang (ICCD, 2000)

VLSI systolic array architecture for the lattice structure of the discrete wavelet transform. - Carlos E. Cabrera Reyes; Javier D. Bruguera (ISCAS, 2000)

Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring. - Elisardo Antelo; Tomás Lang; Javier D. Bruguera (IEEE Trans. Computers, 2000)

Very-High Radix CORDIC Rotation Based on Selection by Rounding. - Elisardo Antelo; Tomás Lang; Javier D. Bruguera (J. VLSI Signal Process., 2000)

Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition. - Javier D. Bruguera; Tomás Lang (IEEE Symposium on Computer Arithmetic, 2001)

Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree. - José-Alejandro Piñeiro; Javier D. Bruguera; Jean-Michel Muller (IEEE Symposium on Computer Arithmetic, 2001)

FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation. - José-Alejandro Piñeiro; Javier D. Bruguera; Jean-Michel Muller (DSD, 2001)

Implementation of a NURBS to Bézier Conversor with Constant Latency. - Paula N. Mallón; Montserrat Bóo; Javier D. Bruguera (FPL, 2001)

COPA: a GIS-based Tool for Land Consolidation Projects. - Juan Touriño; Francisco F. Rivera; Carlos Álvarez; Cesar M. Dans; Jorge Parapar; Ramon Doallo; Marcos Boullón; Javier D. Bruguera; Rafael Crecente; Xesús P. González (ACM-GIS, 2001)

Parallelization of the STEM-II Air Quality Model. - José Carlos Mouriño; David E. Singh; María J. Martín; J. M. Eiroa; Francisco F. Rivera; Ramon Doallo; Javier D. Bruguera (HPCN Europe, 2001)

The STEM-II Air Quality Model on a Distributed Memory System. - José Carlos Mouriño; María J. Martín; Ramon Doallo; David E. Singh; Francisco F. Rivera; Javier D. Bruguera (ICPP Workshops, 2001)

Multilevel reverse most-significant carry computation. - Javier D. Bruguera; Tomás Lang (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Concentric Strips: Algorithms and Architecture for the Compression/Decompression of Triangle Meshes. - Paula N. Mallón; Montserrat Bóo; Margarita Amor; Javier D. Bruguera (3DPVT, 2002)

High-Radix Logarithm with Selection by Rounding. - José-Alejandro Piñeiro; Milos D. Ercegovac; Javier D. Bruguera (ASAP, 2002)

Hardware Implementation of the Subdivision Loop Algorithm. - Ángel del Río; Montserrat Bóo; Margarita Amor; Javier D. Bruguera (EUROMICRO, 2002)

Floating-Point Fused Multiply-Add with Reduced Latency. - Tomás Lang; Javier D. Bruguera (ICCD, 2002)

Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. - José-Alejandro Piñeiro; Milos D. Ercegovac; Javier D. Bruguera (ICCD, 2002)

High-Speed Double-Precision Computation of Reciprocal, Division, Square Root and Inverse Square Root. - José-Alejandro Piñeiro; Javier D. Bruguera (IEEE Trans. Computers, 2002)

High-Radix Iterative Algorithm for Powering Computation. - José-Alejandro Piñeiro; Milos D. Ercegovac; Javier D. Bruguera (IEEE Symposium on Computer Arithmetic, 2003)

On-line high-radix exponential with selection by rounding. - José-Alejandro Piñeiro; Javier D. Bruguera; Milos D. Ercegovac (ISCAS (4), 2003)

Adaptive Tessellation of NURBS Surfaces. - F. J. Espino; Montserrat Bóo; Margarita Amor; Javier D. Bruguera (WSCG, 2003)

Research Article: A GIS-embedded system to support land consolidation plans in Galicia. - Juan Touriño; Jorge Parapar; Ramon Doallo; Marcos Boullón; Francisco F. Rivera; Javier D. Bruguera; Xesús P. González; Rafael Crecente; Carlos Álvarez (Int. J. Geogr. Inf. Sci., 2003)

Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor. - Daniel Piso Fernandez; José-Alejandro Piñeiro; Javier D. Bruguera (J. Syst. Archit., 2003)

High performance air pollution modeling for a power plant environment. - María J. Martín; David E. Singh; José Carlos Mouriño; Francisco F. Rivera; Ramon Doallo; Javier D. Bruguera (Parallel Comput., 2003)

Multilevel Reverse-Carry Addition: Single and Dual Adders. - Javier D. Bruguera; Tomás Lang (J. VLSI Signal Process., 2003)

Arithmetic Coding Architecture for H.264/AVC CABAC Compression System. - Roberto R. Osorio; Javier D. Bruguera (DSD, 2004)

Algorithms and Hardware for Data Compression in Point Rendering Applications. - Paula N. Mallón; Montserrat Bóo; Margarita Amor; Javier D. Bruguera (WSCG (Short Papers), 2004)

Floating-Point Multiply-Add-Fused with Reduced Latency. - Tomás Lang; Javier D. Bruguera (IEEE Trans. Computers, 2004)

Algorithm and Architecture for Logarithm, Exponential, and Powering Computation. - José-Alejandro Piñeiro; Milos D. Ercegovac; Javier D. Bruguera (IEEE Trans. Computers, 2004)

Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition. - Javier D. Bruguera; Tomás Lang (IEEE Symposium on Computer Arithmetic, 2005)

A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder. - Roberto R. Osorio; Javier D. Bruguera (DSD, 2005)

Adaptive Tessellation of Bezier Surfaces Based on Displacement Maps. - F. J. Espino; Montserrat Bóo; Margarita Amor; Javier D. Bruguera (WSCG (Short Papers), 2005)

High-Speed Function Approximation Using a Minimax Quadratic Interpolator. - José-Alejandro Piñeiro; Stuart F. Oberman; Jean-Michel Muller; Javier D. Bruguera (IEEE Trans. Computers, 2005)

High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation. - José-Alejandro Piñeiro; Milos D. Ercegovac; Javier D. Bruguera (J. VLSI Signal Process., 2005)

A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization. - Javier D. Bruguera; Roberto R. Osorio (DSD, 2006)

A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table. - Viay Holimath; Javier D. Bruguera (DSD, 2006)

A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems. - Roberto R. Osorio; Javier D. Bruguera (DSD, 2006)

High-Throughput Architecture for H.264/AVC CABAC Compression System. - Roberto R. Osorio; Javier D. Bruguera (IEEE Trans. Circuits Syst. Video Technol., 2006)

Entropy Coding on a Programmable Processor Array for Multimedia SoC. - Roberto R. Osorio; Javier D. Bruguera (ASAP, 2007)

Hardware support for adaptive tessellation of Bézier surfaces based on local tests. - F. J. Espino; Montserrat Bóo; Margarita Amor; Javier D. Bruguera (J. Syst. Archit., 2007)

A Digit-by-Digit Algorithm for mth Root Extraction. - Paolo Montuschi; Javier D. Bruguera; Luigi Ciminiera; José-Alejandro Piñeiro (IEEE Trans. Computers, 2007)

Forcing one-sided results in Goldschmidt algorithm. - Daniel Piso Fernandez; Javier D. Bruguera (ACSCC, 2008)

An FPGA architecture for CABAC decoding in manycore systems. - Roberto R. Osorio; Javier D. Bruguera (ASAP, 2008)

A New Rounding Algorithm for Variable Latency Division and Square Root Implementations. - Daniel Piso Fernandez; Javier D. Bruguera (DSD, 2008)

Topic 10: Parallel Numerical Algorithms. - Hans-Joachim Bungartz; Javier D. Bruguera; Peter Arbenz; Bruce Hendrickson (Euro-Par, 2008)

A Radix-2 Digit-by-Digit Architecture for Cube Root. - Alex Piñeiro; Javier D. Bruguera; Fabrizio Lamberti; Paolo Montuschi (IEEE Trans. Computers, 2008)

Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation. - Daniel Piso Fernandez; Javier D. Bruguera (DSD, 2009)

High Performance Image Processing on a Massively Parallel Processor Array. - Roberto R. Osorio; Cesar Diaz-Resco; Javier D. Bruguera (DSD, 2009)

Composite Iterative Algorithm and Architecture for q-th Root Calculation. - Álvaro Vázquez; Javier D. Bruguera (IEEE Symposium on Computer Arithmetic, 2011)

Guest Editors' Introduction: Special Section on Computer Arithmetic. - Javier D. Bruguera; Marius Cornea; Debjit Das Sarma (IEEE Trans. Computers, 2011)

Variable Latency Goldschmidt Algorithm Based on a New Rounding Method and a Remainder Estimate. - Daniel Piso Fernandez; Javier D. Bruguera (IEEE Trans. Computers, 2011)

GPU-based Visualization of Hybrid Terrain Models. - E. G. Paredes; Montserrat Bóo; Margarita Amor; Jürgen Döllner; Javier D. Bruguera (GRAPP/IVAPP, 2012)

Extended hybrid meshing algorithm for multiresolution terrain models. - E. G. Paredes; Montserrat Bóo; Margarita Amor; Javier D. Bruguera; Jürgen Döllner (Int. J. Geogr. Inf. Sci., 2012)

8th Conference on Real Numbers and Computers. - Marc Daumas; Javier D. Bruguera (Inf. Comput., 2012)

FlexSig: Implementing flexible hardware signatures. - Lois Orosa 001; Elisardo Antelo; Javier D. Bruguera (ACM Trans. Archit. Code Optim., 2012)

Iterative Algorithm and Architecture for Exponential, Logarithm, Powering, and Root Extraction. - Álvaro Vázquez; Javier D. Bruguera (IEEE Trans. Computers, 2013)

High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard. - Roberto R. Osorio; Javier D. Bruguera (J. Signal Process. Syst., 2013)

A New Rounding Method Based on Parallel Remainder Estimation for Goldschmidt and Newton-Raphson Algorithms. - Daniel Piso Fernandez; Javier Diaz Bruguera (DSD, 2014)

Obtaining Accurate Error Expressions and Bounds for Floating-Point Multiplicative Algorithms. - Daniel Piso Fernandez; Javier D. Bruguera (Comput. J., 2014)

Optimizing the representation of intervals. - Javier D. Bruguera (Sci. Comput. Program., 2014)

Fast Radix-10 Multiplication Using Redundant BCD Codes. - Álvaro Vázquez; Elisardo Antelo; Javier D. Bruguera (IEEE Trans. Computers, 2014)

Asymmetric Allocation in a Shared Flexible Signature Module for Multicore Processors. - Lois Orosa 001; Javier D. Bruguera; Elisardo Antelo (Comput. J., 2016)

Hybrid terrain rendering based on the external edge primitive. - E. G. Paredes; Margarita Amor; Montserrat Bóo; Javier D. Bruguera; Jürgen Döllner (Int. J. Geogr. Inf. Sci., 2016)

Radix-64 Floating-Point Divider. - Javier D. Bruguera (ARITH, 2018)

Guest Editors Introduction: Special Section on Computer Arithmetic. - Javier D. Bruguera; Florent de Dinechin (IEEE Trans. Computers, 2019)

Low Latency Floating-Point Division and Square Root Unit. - Javier D. Bruguera (IEEE Trans. Computers, 2020)

Low-Latency and High-Bandwidth Pipelined Radix-64 Division and Square Root Unit. - Javier D. Bruguera (ARITH, 2022)

Formal Verification of a Chained Multiply-Add Design: Combining Theorem Proving and Equivalence Checking. - David M. Russinoff; Javier D. Bruguera; Cuong Chau; Mayank Manjrekar; Nicholas Pfister; Harsha Valsaraju (ARITH, 2022)

Radix-64 Floating-Point Division and Square Root: Iterative and Pipelined Units. - Javier D. Bruguera (IEEE Trans. Computers, 2023)