Analytical Performance Modeling of Hierarchical Interconnect Fabrics. - Nikita Nikitin; Javier de San Pedro; Josep Carmona 001; Jordi Cortadella (NOCS, 2012)

Integrating formal verification in an online judge for e-Learning logic circuit design. - Javier de San Pedro; Josep Carmona 001; Jordi Cortadella; Jordi Petit (SIGCSE, 2012)

Physical-aware system-level design for tiled hierarchical chip multiprocessors. - Jordi Cortadella; Javier de San Pedro; Nikita Nikitin; Jordi Petit (ISPD, 2013)

Physical planning for the architectural exploration of large-scale chip multiprocessors. - Javier de San Pedro; Nikita Nikitin; Jordi Cortadella; Jordi Petit (NOCS, 2013)

Architectural Exploration of Large-Scale Hierarchical Chip Multiprocessors. - Nikita Nikitin; Javier de San Pedro; Jordi Cortadella (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

A hierarchical approach for generating regular floorplans. - Javier de San Pedro; Jordi Cortadella; Antoni Roca 001 (ICCAD, 2014)

Log-Based Simplification of Process Models. - Javier de San Pedro; Josep Carmona 001; Jordi Cortadella (BPM, 2015)

Specification Mining for Asynchronous Controllers. - Javier de San Pedro; Thomas Bourgeat; Jordi Cortadella (ASYNC, 2016)

Discovering Duplicate Tasks in Transition Systems for the Simplification of Process Models. - Javier de San Pedro; Jordi Cortadella (BPM, 2016)

Mining structured petri nets for the visualization of process behavior. - Javier de San Pedro; Jordi Cortadella (SAC, 2016)

Structure discovery techniques for circuit design and process model visualization. - Javier de San Pedro (2017)