TARS: A toolbox for statistical reliability modeling of CMOS devices. - Javier Diaz-Fortuny; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (SMACD, 2017)

A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging. - Javier Diaz-Fortuny; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001; Enrique Barajas; Xavier Aragonès; Diego Mateo (SMACD, 2017)

CMOS Characterization and Compact Modelling for Circuit Reliability Simulation. - Javier Diaz-Fortuny; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (IOLTS, 2018)

Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability. - Victor M. van Santen; Javier Diaz-Fortuny; Hussam Amrouch; Javier Martín-Martínez; Rosana Rodríguez; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001; Jörg Henkel; Montserrat Nafría (IRPS, 2018)

A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation. - Javier Diaz-Fortuny; Pablo Saraza-Canflanca; Antonio Toro-Frías; Rafael Castro-López; Javier Martín-Martínez; Elisenda Roca; Rosana Rodríguez; Francisco V. Fernández 001; Montserrat Nafría (SMACD, 2018)

Automated Massive RTN Characterization Using a Transistor Array Chip. - Pablo Saraza-Canflanca; Javier Diaz-Fortuny; Antonio Toro-Frías; Rafael Castro-López; Elisenda Roca; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (SMACD, 2018)

Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models. - Pablo Saraza-Canflanca; D. Malagon; Fábio Passos; A. Toro; Juan Núñez 002; Javier Diaz-Fortuny; Rafael Castro-López; Elisenda Roca; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (SMACD, 2018)

New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors. - Pablo Saraza-Canflanca; Javier Diaz-Fortuny; Rafael Castro-López; Elisenda Roca Moreno; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (DATE, 2019)

A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices. - G. Pedreira; Javier Martín-Martínez; Javier Diaz-Fortuny; Pablo Saraza-Canflanca; Rosana Rodríguez; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001; Montserrat Nafría (IRPS, 2019)

TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level. - Pablo Saraza-Canflanca; Javier Diaz-Fortuny; Rafael Castro-López; Elisenda Roca; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (SMACD, 2019)

A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI. - Javier Diaz-Fortuny; Javier Martín-Martínez; Rosana Rodríguez; Rafael Castro-López; Elisenda Roca; Xavier Aragonès; Enrique Barajas; Diego Mateo; Francisco V. Fernández 001; Montserrat Nafría (IEEE J. Solid State Circuits, 2019)

A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level. - Pablo Saraza-Canflanca; Javier Diaz-Fortuny; Rafael Castro-López; Elisenda Roca; Javier Martín-Martínez; Rosana Rodríguez; Montserrat Nafría; Francisco V. Fernández 001 (Integr., 2020)

Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits. - Javier Diaz-Fortuny; Pablo Saraza-Canflanca; Rafael Castro-López; Elisenda Roca; Javier Martín-Martínez; Rosana Rodríguez; Francisco V. Fernández 001; Montserrat Nafría (IEEE Trans. Instrum. Meas., 2020)

A Ring-Oscillator-Based Degradation Monitor Concept with Tamper Detection Capability. - Javier Diaz-Fortuny; Pablo Saraza-Canflanca; Erik Bury; Michiel Vandemaele; Ben Kaczer; Robin Degraeve (IRPS, 2022)

A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies. - Pablo Saraza-Canflanca; Héctor Carrasco-Lopez; Andrés Santana-Andreo; Javier Diaz-Fortuny; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (IRPS, 2022)

Reliability challenges in Forksheet Devices: (Invited Paper). - Erik Bury; Michiel Vandemaele; Jacopo Franco; Adrian Chasin; Stanislav Tyaginov; A. Vandooren; Romain Ritzenthaler; Hans Mertens; Javier Diaz-Fortuny; N. Horiguchi; Dimitri Linten; Ben Kaczer (IRPS, 2023)

Improving the Tamper-Aware Odometer Concept by Enhancing Dynamic Stress Operation. - Javier Diaz-Fortuny; Dishant Sangani; Pablo Saraza-Canflanca; Erik Bury; Robin Degraeve; Ben Kaczer (IRPS, 2023)

Challenges and solutions to the defect-centric modeling and circuit simulation of time-dependent variability. - Javier Martín-Martínez; Javier Diaz-Fortuny; Pablo Saraza-Canflanca; Rosana Rodríguez; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001; Montserrat Nafría (IRPS, 2023)

The Role of Mobility Degradation in the BTI-Induced RO Aging in a 28-nm Bulk CMOS Technology: (Student paper). - Dishant Sangani; Javier Diaz-Fortuny; Erik Bury; Ben Kaczer; Georges G. E. Gielen (IRPS, 2023)

Using dedicated device arrays for the characterization of TDDB in a scaled HK/MG technology. - Pablo Saraza-Canflanca; Javier Diaz-Fortuny; Andrea Vici; Erik Bury; Robin Degraeve; Ben Kaczer (IRPS, 2023)

Machine Learning Unleashes Aging and Self-Heating Effects: From Transistors to Full Processor (Invited Paper). - Hussam Amrouch; Victor M. van Santen; Javier Diaz-Fortuny; Florian Klemme (IRPS, 2024)

Demonstration of Chip Overclock Detection by Employing Tamper-Aware Odometer Technology. - Javier Diaz-Fortuny; Pablo Saraza-Canflanca; Alex Romano-Molar; Erik Bury; Robin Degraeve; Ben Kaczer (IRPS, 2024)

Statistical Characterization of Off-State Stress Degradation in Planar HKMG nFETs Using Device Arrays. - Pablo Saraza-Canflanca; Dishant Sangani; Javier Diaz-Fortuny; Stanislav Tyaginov; Georges G. E. Gielen; Erik Bury; Ben Kaczer (IRPS, 2024)

Transistor Aging and Circuit Reliability at Cryogenic Temperatures. - Javier Diaz-Fortuny; Vishal Nayar (DATE, 2025)

When Variability Meets Security. - Rafael Castro-López; Javier Diaz-Fortuny; Elisenda Roca; Francisco V. Fernández 001 (IRPS, 2025)

Investigation of Cryogenic Aging in 28 nm CMOS: Suppression of BTI and HCD in Circuits and SRAM. - Javier Diaz-Fortuny; Mahdi Benkhelifa; Alexander Grill; Erik Bury; Robin Degraeve; Ben Kaczer; Hussam Amrouch (IRPS, 2025)

A Ring-Oscillator-based Odometer to Unveil the Actual IC Usage Time. - F. de Los Santos-Prieto; Javier Diaz-Fortuny; Rafael Castro-López; Elisenda Roca; F. V. Fernandez (ISCAS, 2025)