A 55nm CMOS Linearized Oscillator for Audio VCO-ADCs achieving 78dBA of SNDR with $153 mu mathrm{W}$. - Rubén Garvi; Javier Granizo; Angel Salvador; Luis Hernández 003 (ICECS 2022, 2022)

Validation of a CMOS SNN network based on a time-domain threshold neuron circuit achieving 114.90 pJ/inference on MNIST. - Diego Garcia; Javier Granizo; Luis Hernández 003 (AICAS, 2023)

A CMOS LIF neuron based on a charge-powered oscillator with time-domain threshold logic. - Javier Granizo; Rubén Garvi; Diego Garcia; Luis Hernández 003 (ISCAS, 2023)

A VCO-ADC Linearized by a Capacitive Frequency-to-Current Converter. - Rubén Garvi; Javier Granizo; Eric Gutierrez; Victor Medina; Andreas Wiesbauer; Luis Hernández 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Scalable and PVT Invariant Spiking Neuron Using Asynchronous CMOS Logic. - Dante Loi; Javier Granizo; Luis Hernández 003 (ISCAS, 2024)

A Second-Order Audio VCO-ADC with 103-dB-A Dynamic Range and Binary-Weighted Internal Architecture. - Victor Medina; Rubén Garvi; Javier Granizo; Pedro Amaral; Luis Hernández 003 (CoRR, 2024)

Analysis of Clock Jitter in VCO-ADCs Under Presence of Mismatch and Blocking Signals. - Javier Granizo; Victor Medina; Luis Hernández 003; Rubén Garvi (ISCAS, 2025)

Second-Order VCO-ADC Architecture With Low-Area and High Dynamic Range Using Internal Binary Encoding. - Victor Medina; Rubén Garvi; Javier Granizo; Pedro Amaral; Luis Hernandez Corporales (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)