A Hardware Approach to Interval Arithmetic for Sine and Cosine Functions. - Javier Hormigo; Julio Villalba; Emilio L. Zapata (SCAN, 1998)

High resolution spectral analysis of images using the pseudo-Wigner distribution. - Javier Hormigo; Gabriel Cristóbal (IEEE Trans. Signal Process., 1998)

Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm. - Javier Hormigo; Julio Villalba; Emilio L. Zapata (IEEE Symposium on Computer Arithmetic, 1999)

Arithmetic Unit for the Computation of Interval Elementary Functions. - Javier Hormigo; Julio Villalba; Emilio L. Zapata (EUROMICRO, 1999)

Texture segmentation through eigen-analysis of the Pseudo-Wigner distribution. - Gabriel Cristóbal; Javier Hormigo (Pattern Recognit. Lett., 1999)

A Hardware Algorithm for Variable-Precision Logarithm. - Javier Hormigo; Julio Villalba; Michael J. Schulte (ASAP, 2000)

MMX-Like Architecture Extension to Support the Rotation Operation. - Julio Villalba; Javier Hormigo; Mario A. González; Emilio L. Zapata (IEEE International Conference on Multimedia and Expo (III), 2000)

Polynomial Evaluation on Multimedia Processors. - Julio Villalba; Gerardo Bandera; Mario A. González; Javier Hormigo; Emilio L. Zapata (ASAP, 2002)

Texture segmentation and analysis using local spectral methods. - Gabriel Cristóbal; Sylvain Fischer; Manuel Forero-Vargas; Rafael Redondo; Javier Hormigo (ISSPA (1), 2003)

Minimum Sum of Absolute Differences Implementation in a Single FPGA Device. - Joaquín Olivares 001; Javier Hormigo; Julio Villalba; Ignacio Benavides (FPL, 2004)

Evaluation of Elementary Functions Using Multimedia Features. - Gerardo Bandera; Mario A. González; Julio Villalba; Javier Hormigo; Emilio L. Zapata (IPDPS, 2004)

CORDIC Processor for Variable-Precision Interval Arithmetic. - Javier Hormigo; Julio Villalba; Emilio L. Zapata (J. VLSI Signal Process., 2004)

On-line Multioperand Addition Based on On-line Full Adders. - Julio Villalba; Javier Hormigo; Jose M. Prades; Emilio L. Zapata (ASAP, 2005)

Pipelined Range Reduction for Floating Point Numbers. - Francisco J. Jaime; Julio Villalba; Javier Hormigo; Emilio L. Zapata (ASAP, 2006)

Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA. - Joaquín Olivares 001; Ignacio Benavides; Javier Hormigo; Julio Villalba; Emilio L. Zapata (FPL, 2006)

SAD computation based on online arithmetic for motion estimation. - Joaquín Olivares 001; Javier Hormigo; Julio Villalba; Ignacio Benavides; Emilio L. Zapata (Microprocess. Microsystems, 2006)

Improving the Throughput of On-line Addition for Data Streams. - Julio Villalba; Javier Hormigo; Tomás Lang (ASAP, 2007)

SIMD Enhancements for a Hough Transform Implementation. - Francisco J. Jaime; Javier Hormigo; Julio Villalba; Emilio L. Zapata (DSD, 2008)

New SIMD instructions set for image processing applications enhancement. - Francisco J. Jaime; Javier Hormigo; Julio Villalba; Emilio L. Zapata (ICIP, 2008)

Pipelined Architecture for Additive Range Reduction. - Francisco J. Jaime; Julio Villalba; Javier Hormigo; Emilio L. Zapata (J. Signal Process. Syst., 2008)

Efficient Implementation of Carry-Save Adders in FPGAs. - Javier Hormigo; Manuel Ortiz; Francisco J. Quiles 002; Francisco J. Jaime; Julio Villalba; Emilio L. Zapata (ASAP, 2009)

Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator. - Carlos Diego Moreno-Moreno; Francisco J. Quiles 002; Manuel Ortiz; María Brox; Javier Hormigo; Julio Villalba; Emilio L. Zapata (ICECS, 2009)

UCORE: Reconfigurable Platform for Educational Purposes. - Francisco J. Quiles 002; Manuel Ortiz; María Brox; Carlos Diego Moreno-Moreno; Javier Hormigo; Julio Villalba (ReConFig, 2010)

CORDIC-based LMMSE equalizer for Software Defined Radio. - Murugappan Senthilvelan; Javier Hormigo; Joon Hwa Chun; Mihai Sima; Daniel Iancu; Michael J. Schulte; John Glossner (ICSAMOS, 2010)

Enhanced Scaling-Free CORDIC. - Francisco J. Jaime; Miguel A. Sanchez; Javier Hormigo; Julio Villalba; Emilio L. Zapata (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Convolution Computation in FPGA Based on Carry-Save Adders and Circular Buffers. - Carlos Diego Moreno-Moreno; Pilar Martínez; Francisco Bellido 001; Javier Hormigo; Manuel Ortiz; Francisco J. Quiles 002 (IT Revolutions, 2011)

High-Speed Algorithms and Architectures for Range Reduction Computation. - Francisco J. Jaime; M. A. Sánchez; Javier Hormigo; Julio Villalba; Emilio L. Zapata (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A study of decimal left shifters for binary numbers. - Sonia González-Navarro; Javier Hormigo; Michael J. Schulte (Inf. Comput., 2012)

Radix-2 Multioperand and Multiformat Streaming Online Addition. - Julio Villalba; Tomás Lang; Javier Hormigo (IEEE Trans. Computers, 2012)

Efficient floating-point representation for balanced codes for FPGA devices. - Julio Villalba; Javier Hormigo; Francisco Corbera; Mario A. González; Emilio L. Zapata (ICCD, 2013)

Multioperand Redundant Adders on FPGAs. - Javier Hormigo; Julio Villalba; Emilio L. Zapata (IEEE Trans. Computers, 2013)

Self-Reconfigurable Constant Multiplier for FPGA. - Javier Hormigo; Gabriel Caffarena; Juan P. Oliver; Eduardo I. Boemo (ACM Trans. Reconfigurable Technol. Syst., 2013)

Optimizing DSP circuits by a new family of arithmetic operators. - Javier Hormigo; Julio Villalba (ACSSC, 2014)

Simplified floating-point units for high dynamic range image and video systems. - Javier Hormigo; Julio Villalba (ISCE, 2015)

Improving fixed-point implementation of QR decomposition by rounding-to-nearest. - Sergio D. Muñoz; Javier Hormigo (ISCE, 2015)

High-Throughput FPGA Implementation of QR Decomposition. - Sergio D. Muñoz; Javier Hormigo (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

New Formats for Computing with Real-Numbers under Round-to-Nearest. - Javier Hormigo; Julio Villalba (IEEE Trans. Computers, 2016)

Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest. - Javier Hormigo; Julio Villalba (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Normalizing or Not Normalizing? An Open Question for Floating-Point Arithmetic in Embedded Systems. - Sonia González-Navarro; Javier Hormigo (ARITH, 2017)

Floating Point Square Root under HUB Format. - Julio Villalba-Moreno; Javier Hormigo (ICCD, 2017)

Introduction to the Special Issue on Computer Arithmetic. - Javier Hormigo; Jean-Michel Muller; Stuart F. Oberman; Nathalie Revol; Arnaud Tisserand; Julio Villalba-Moreno (IEEE Trans. Computers, 2017)

HUB Floating Point for Improving FPGA Implementations of DSP Applications. - Javier Hormigo; Julio Villalba (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Unbiased Rounding for HUB Floating-Point Addition. - Julio Villalba-Moreno; Javier Hormigo; Sonia González-Navarro (IEEE Trans. Computers, 2018)

Reproducible Summation Under HUB Format. - Julio Villalba-Moreno; Javier Hormigo; Francisco J. Jaime (ARITH, 2019)

Designing a Project for Learning Industry 4.0 by Applying IoT to Urban Garden. - Javier Hormigo; Andrés Rodríguez 001 (Rev. Iberoam. de Tecnol. del Aprendiz., 2019)

Fast HUB Floating-Point Adder for FPGA. - Julio Villalba; Javier Hormigo; Sonia González-Navarro (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Floating-Point Fused Multiply-Add under HUB Format. - Javier Hormigo; Julio Villalba-Moreno; Sonia Gonzalez-Navarro (ARITH, 2020)

New Results on Non-Normalized Floating-Point Formats. - Sonia González-Navarro; Javier Hormigo (IEEE Trans. Computers, 2020)

FPGA acceleration of bit-true simulations for word-length optimization. - Javier Hormigo; Gabriel Caffarena (ARITH, 2021)

Efficient Floating-Point Givens Rotation Unit. - Javier Hormigo; Sergio D. Muñoz (Circuits Syst. Signal Process., 2021)

High-Radix Formats for Enhancing Floating-Point FPGA Implementations. - Julio Villalba; Javier Hormigo (Circuits Syst. Signal Process., 2022)

High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS. - Marco Hormigo-Jiménez; Javier Hormigo (DCIS, 2023)

Computing DTWs on CPU, GPU and FPGA with SYCL. - Cristian Campos; Rafael Asenjo; Javier Hormigo; Angeles G. Navarro (Euro-Par Workshops (1), 2024)

HUB Meets Posit: Arithmetic Units Implementation. - Raul Murillo 001; Javier Hormigo; Alberto A. Del Barrio; Guillermo Botella (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Leveraging SYCL for Heterogeneous cDTW Computation on CPU, GPU, and FPGA. - Cristian Campos; Rafael Asenjo; Javier Hormigo; Angeles G. Navarro (Concurr. Comput. Pract. Exp., 2025)

Advanced Quantization Schemes to Increase Accuracy, Reduce Area, and Lower Power Consumption in FFT Architectures. - Mario Garrido; Víctor Manuel Bautista; Alejandro Portas; Javier Hormigo (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)