CMOS single-ended-to-differential low-noise amplifier. - Tomás Carrasco Carrillo; José Gabriel Macias-Montero; Aitor Osorio Martí; Javier Sieiro Córdoba; José María López-Villegas (Integr., 2009)

Optimized passive devices for low-power LNA design. - Ignacio Gil; Raúl Fernández; Javier J. Sieiro; José María López-Villegas (ICECS, 2010)

Low-power current-reused RF front-end based on optimized transformers topology. - Ignacio Gil; Ignasi Cairó; Javier J. Sieiro; José María López-Villegas (Integr., 2010)

Compact class-AB follower for wideband closed loop line drivers. - David Gascon; Andreu Sanuy; Javier J. Sieiro (ICECS, 2012)

Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors. - Reinier Gonzalez-Echevarria; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001; Javier J. Sieiro; Neus Vidal; José María López-Villegas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Introduction to the special issue on Radio Frequency Integrated Circuits (RFIC) design techniques. - Elisenda Roca; Javier J. Sieiro (Integr., 2016)

Extending the frequency range of quasi-static electromagnetic solvers. - Saiyd Ahyoune; Javier J. Sieiro; Tomás Carrasco Carrillo; Neus Vidal; José María López-Villegas; Elisenda Roca; Francisco V. Fernández 001 (SMACD, 2017)

An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors. - Reinier Gonzalez-Echevarria; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001; Javier J. Sieiro; José María López-Villegas; Neus Vidal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Fabrication of Full-3D Printed Electronics RF Passive Components and Circuits. - Arnau Salas Barenys; Neus Vidal; Javier J. Sieiro; José María López-Villegas; B. Medina-Rodriguez; F. M. Ramos (PRIME, 2018)

Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator. - Saiyd Ahyoune; Javier J. Sieiro; Tomás Carrasco Carrillo; Neus Vidal; José María López-Villegas; Elisenda Roca; Francisco V. Fernández 001 (Integr., 2018)

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. - Ricardo Martins 003; Nuno Lourenço 003; Fábio Passos; Ricardo Povoa; António Canelas; Elisenda Roca; Rafael Castro-López; Javier J. Sieiro; Francisco V. Fernández 001; Nuno Horta (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology. - Fábio Passos; Elisenda Roca; Ricardo Martins 003; Nuno Lourenço 003; Saiyd Ahyoune; Javier J. Sieiro; Rafael Castro-López; Nuno Horta; Francisco V. Fernández 001 (IEEE Access, 2020)

A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems. - Fábio Passos; Elisenda Roca; Javier J. Sieiro; Rafaella Fiorelli; Rafael Castro-López; José María López-Villegas; Francisco V. Fernández 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)