Deconstructing bus access control policies for Real-Time multicores. - Javier Jalle; Jaume Abella 001; Eduardo Quiñones; Luca Fossati; Marco Zulianello; Francisco J. Cazorla (SIES, 2013)

Bus designs for time-probabilistic multicore processors. - Javier Jalle; Leonidas Kosmidis; Jaume Abella 001; Eduardo Quiñones; Francisco J. Cazorla (DATE, 2014)

AHRB: A high-performance time-composable AMBA AHB bus. - Javier Jalle; Jaume Abella 001; Eduardo Quiñones; Luca Fossati; Marco Zulianello; Francisco J. Cazorla (RTAS, 2014)

A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study. - Javier Jalle; Eduardo Quiñones; Jaume Abella 001; Luca Fossati; Marco Zulianello; Francisco J. Cazorla (RTSS, 2014)

Increasing confidence on measurement-based contention bounds for real-time round-robin buses. - Gabriel Fernandez 002; Javier Jalle; Jaume Abella 001; Eduardo Quiñones; Tullio Vardanega; Francisco J. Cazorla (DAC, 2015)

Resource usage templates and signatures for COTS multicore processors. - Gabriel Fernandez 002; Javier Jalle; Jaume Abella 001; Eduardo Quiñones; Tullio Vardanega; Francisco J. Cazorla (DAC, 2015)

Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems. - David Trilla; Javier Jalle; Mikel Fernández; Jaume Abella 001; Francisco J. Cazorla (RTAS, 2016)

Contention-aware performance monitoring counte support for real-time MPSoCs. - Javier Jalle; Mikel Fernández; Jaume Abella 001; Jan Andersson; Mathieu Patte; Luca Fossati; Marco Zulianello; Francisco J. Cazorla (SIES, 2016)

Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems. - Javier Jalle; Eduardo Quiñones; Jaume Abella 001; Luca Fossati; Marco Zulianello; Francisco J. Cazorla (SIES, 2016)

Improving time predictability of shared hardware resources in real-time multicore systems : emphasis on the space domain. - Javier Jalle (2016)

Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration. - Gabriel Fernandez 002; Javier Jalle; Jaume Abella 001; Eduardo Quiñones; Tullio Vardanega; Francisco J. Cazorla (IEEE Trans. Computers, 2017)