A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems. - Andrés Otero; Rubén Salvador; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (AHS, 2011)

Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (AHS, 2011)

Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Lukás Sekanina; Teresa Riesgo (ReConFig, 2011)

Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (FPL, 2012)

A noise-agnostic self-adaptive image processing application based on evolvable hardware. - Javier Mora 001; Angel Gallego; Andrés Otero; Blanca López; Eduardo de la Torre; Teresa Riesgo (DASIP, 2013)

Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform. - Javier Mora 001; Angel Gallego; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (DASIP, 2013)

A self-adaptive image processing application based on evolvable and scalable hardware. - Angel Gallego; Javier Mora 001; Andrés Otero; Blanca López; Eduardo de la Torre; Teresa Riesgo (FPL, 2013)

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays. - Angel Gallego; Javier Mora 001; Andrés Otero; Rubén Salvador; Eduardo de la Torre; Teresa Riesgo (IPDPS Workshops, 2013)

A scalable evolvable hardware processing array. - Angel Gallego; Javier Mora 001; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (ReConFig, 2013)

Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (IEEE Trans. Computers, 2013)

Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. - Javier Mora 001; Andrés Otero; Eduardo de la Torre; Teresa Riesgo (ReCoSoC, 2015)

IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado. - Rafael Zamacola; Alberto García-Martínez; Javier Mora 001; Andrés Otero; Eduardo de la Torre (ReConFig, 2018)

Accelerating the evolution of a systolic array-based evolvable hardware system. - Javier Mora 001; Eduardo de la Torre (Microprocess. Microsystems, 2018)

Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems. - Rafael Zamacola; Alberto García-Martínez; Javier Mora 001; Andrés Otero; Eduardo de la Torre (FCCM, 2019)

On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming. - Javier Mora 001; Rubén Salvador; Eduardo de la Torre (Genet. Program. Evolvable Mach., 2019)