FPGA implementation of a strong Reversi player. - Javier Olivito; Carlos González 002; Javier Resano (FPT, 2010)

An FPGA-based specific processor for Blokus Duo. - Javier Olivito; Carlos González 002; Javier Resano (FPT, 2013)

An improved FPGA-based specific processor for Blokus Duo. - Javier Olivito; Alberto Delmas; Javier Resano (FPT, 2014)

Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors. - Javier Olivito; Ruben Gran; Javier Resano; Carlos González 002; Enrique F. Torres (Microprocess. Microsystems, 2015)

Accelerating Board Games Through Hardware/Software Codesign. - Javier Olivito; Javier Resano; José Luis Briz (IEEE Trans. Comput. Intell. AI Games, 2017)

Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array. - Javier Olivito; Felipe Serrano 002; Juan Antonio Clemente; Hortensia Mecha; Javier Resano (IET Comput. Digit. Tech., 2018)

Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems. - Adrián Alcolea Morena; Javier Olivito; Javier Resano; Hortensia Mecha (IEEE Trans. Very Large Scale Integr. Syst., 2020)