Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems. - Javier Resano; Diederik Verkest; Daniel Mozos; Serge Vernalde; Francky Catthoor (ESTIMedia, 2003)

Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms. - Javier Resano; Diederik Verkest; Daniel Mozos; Serge Vernalde; Francky Catthoor (FCCM, 2003)

Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems. - Javier Resano; Daniel Mozos; Diederik Verkest; Serge Vernalde; Francky Catthoor (FPL, 2003)

A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements. - Javier Resano; Daniel Mozos; Elena Pérez-Miñana; Hortensia Mecha; Julio Septién (PATMOS, 2003)

Analyzing communication overheads during hardware/software partitioning. - Javier Resano; M. Elena Pérez; Daniel Mozos; Hortensia Mecha; Julio Septién (Microelectron. J., 2003)

Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware. - Javier Resano; Daniel Mozos (DAC, 2004)

A Specific Scheduling Flow for Dynamically Reconfigurable Hardware. - Javier Resano (FPL, 2004)

A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. - Javier Resano; Diederik Verkest; Daniel Mozos; Serge Vernalde; Francky Catthoor (Microprocess. Microsystems, 2004)

A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware. - Javier Resano; Daniel Mozos; Francky Catthoor (DATE, 2005)

A Reconfiguration Manager for Dynamically Reconfigurable Hardware. - Javier Resano; Daniel Mozos; Diederik Verkest; Francky Catthoor (IEEE Des. Test Comput., 2005)

A Dual Cache for Performance and Energy Aware Reconfigurable HW. - Elena Perez Ramo; Javier Resano (FPL, 2006)

A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead. - Elena Perez Ramo; Javier Resano; Daniel Mozos; Francky Catthoor (IPDPS, 2006)

Reducing the reconfiguration overhead: a survey of techniques. - Elena Perez Ramo; Javier Resano; Daniel Mozos; Francky Catthoor (ERSA, 2007)

HW implementation of an execution manager for reconfigurable systems. - Javier Resano; Juan Antonio Clemente; Carlos González 002; Jose Luis Garcia; Daniel Mozos (ERSA, 2007)

Memory hierarchy for high-performance and energyaware reconfigurable systems. - Elena Perez Ramo; Javier Resano; Daniel Mozos; Francky Catthoor (IET Comput. Digit. Tech., 2007)

A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems. - Juan Antonio Clemente; Carlos González 002; Javier Resano; Daniel Mozos (ReConFig, 2008)

Efficiently scheduling runtime reconfigurations. - Javier Resano; Juan Antonio Clemente; Carlos González 002; Daniel Mozos; Francky Catthoor (ACM Trans. Design Autom. Electr. Syst., 2008)

FPGA support for satellite computations of hyper spectral images. - Carlos González 002; Daniel Mozos; Javier Resano (FPL, 2009)

FPGA for Computing the Pixel Purity Index Algorithm on Hyperspectral Images. - Carlos González 002; Daniel Mozos; Javier Resano; Antonio Plaza (ERSA, 2010)

FPGA implementation of a strong Reversi player. - Javier Olivito; Carlos González 002; Javier Resano (FPT, 2010)

FPGA Implementation of the Pixel Purity Index Algorithm for Remotely Sensed Hyperspectral Image Analysis. - Carlos González 002; Javier Resano; Daniel Mozos; Antonio Plaza; David Valencia (EURASIP J. Adv. Signal Process., 2010)

A task graph execution manager for reconfigurable multi-tasking systems. - Juan Antonio Clemente; Carlos González 002; Javier Resano; Daniel Mozos (Microprocess. Microsystems, 2010)

Mini workshop - Real World Engineering Projects: Discovery-based curriculum modules for first-year students. - Stephen Williams; Masoud Agah; Luiz A. DaSilva; Kamyar Dezhgosha; Allen B. MacKenzie; Nicky Mostert-Phipps; Sanjay Raman; Javier Resano (FIE, 2011)

A Replacement Technique to Maximize Task Reuse in Reconfigurable Systems. - Juan Antonio Clemente; Daniel Mozos; Javier Resano (IPDPS Workshops, 2011)

A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems. - Juan Antonio Clemente; Javier Resano; Carlos González 002; Daniel Mozos (IEEE Trans. Very Large Scale Integr. Syst., 2011)

FPGA Implementation of Abundance Estimation for Spectral Unmixing of Hyperspectral Data Using the Image Space Reconstruction Algorithm. - Carlos González 002; Javier Resano; Antonio Plaza; Daniel Mozos (IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2012)

FPGA Implementation of the N-FINDR Algorithm for Remotely Sensed Hyperspectral Image Analysis. - Carlos González 002; Daniel Mozos; Javier Resano; Antonio Plaza (IEEE Trans. Geosci. Remote. Sens., 2012)

An FPGA-based specific processor for Blokus Duo. - Javier Olivito; Carlos González 002; Javier Resano (FPT, 2013)

Use of FPGA or GPU-based architectures for remotely sensed hyperspectral image processing. - Carlos González 002; Sergio Sánchez; Abel Paz; Javier Resano; Daniel Mozos; Antonio Plaza (Integr., 2013)

The Promise of Reconfigurable Computing for Hyperspectral Imaging Onboard Systems: A Review and Trends. - Sebastián López; Tanya Vladimirova; Carlos González 002; Javier Resano; Daniel Mozos; Antonio Plaza (Proc. IEEE, 2013)

An improved FPGA-based specific processor for Blokus Duo. - Javier Olivito; Alberto Delmas; Javier Resano (FPT, 2014)

An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems. - Juan Antonio Clemente; Javier Resano; Daniel Mozos (ACM Trans. Embed. Comput. Syst., 2014)

Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems. - Juan Antonio Clemente; Elena Perez Ramo; Javier Resano; Daniel Mozos; Francky Catthoor (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors. - Javier Olivito; Ruben Gran; Javier Resano; Carlos González 002; Enrique F. Torres (Microprocess. Microsystems, 2015)

Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems. - Juan Antonio Clemente; Ruben Gran; Abel Chocano; Carlos del Prado; Javier Resano (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Accelerating Board Games Through Hardware/Software Codesign. - Javier Olivito; Javier Resano; José Luis Briz (IEEE Trans. Comput. Intell. AI Games, 2017)

Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array. - Javier Olivito; Felipe Serrano 002; Juan Antonio Clemente; Hortensia Mecha; Javier Resano (IET Comput. Digit. Tech., 2018)

Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. - Alejandro Valero; Darío Suárez Gracia; Ruben Gran Tejero; Luis M. Ramos; Agustín Navarro-Torres; Adolfo Muñoz 001; Joaquín Ezpeleta; José Luis Briz; Ana C. Murillo; Eduardo Montijano; Javier Resano; María Villarroya-Gaudó; et al. (WCAE@ISCA, 2019)

Inference in Supervised Spectral Classifiers for On-Board Hyperspectral Imaging: An Overview. - Adrián Alcolea; Mercedes Eugenia Paoletti; Juan Mario Haut; Javier Resano; Antonio Plaza (Remote. Sens., 2020)

Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems. - Adrián Alcolea Morena; Javier Olivito; Javier Resano; Hortensia Mecha (IEEE Trans. Very Large Scale Integr. Syst., 2020)

GPU-Friendly Neural Networks for Remote Sensing Scene Classification. - Juan Mario Haut; Adrián Alcolea; Mercedes Eugenia Paoletti; Javier Plaza; Javier Resano; Antonio Plaza (IEEE Geosci. Remote. Sens. Lett., 2022)

Bayesian Neural Networks to Analyze Hyperspectral Datasets Using Uncertainty Metrics. - Adrián Alcolea; Javier Resano (IEEE Trans. Geosci. Remote. Sens., 2022)