Design and FPGA implementation of digit-serial FIR filters. - Javier Valls; Marcos M. Peiró; Trinidad Sansaloni; Eduardo I. Boemo (ICECS, 1998)

A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation. - Marcos Martínez-Peiró; Javier Valls; T. Sansaloni; A. Perez-Pascual; Eduardo I. Boemo (ICECS, 1999)

Efficient complex-number multipliers mapped on FPGA. - A. Perez-Pascual; Javier Valls; Marcos M. Peiró (ICECS, 1999)

Fast FPGA-based pipelined digit-serial/parallel multipliers. - Javier Valls; Trini Sansaloni; Marcos Martínez-Peiró; Eduardo I. Boemo (ISCAS (1), 1999)

FPGA-based digit-serial complex number multiplier-accumulator. - Trinidad Sansaloni; Javier Valls; Keshab K. Parhi (ISCAS, 2000)

FPGA based on-line complex-number multipliers. - A. Perez-Pascual; T. Sansaloni; Javier Valls (ICECS, 2001)

Distributed arithmetic radix-2 butterflies for FPGA. - T. Sansaloni; A. Perez-Pascual; Javier Valls (ICECS, 2001)

High Performance Quadrature Digital Mixers for FPGAs. - Francisco Cardells-Tormo; Javier Valls-Coquillat (FPL, 2002)

Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard. - Francisco Cardells-Tormo; Javier Valls-Coquillat; Vicenc Almenar-Terre; Vicente Torres-Carot (FPL, 2002)

FPGA-based radix-4 butterflies for HIPERLAN/2. - A. Perez-Pascual; T. Sansaloni; Javier Valls (ISCAS (3), 2002)

Evaluation of CORDIC Algorithms for FPGA Design. - Javier Valls; Martin Kuhlmann; Keshab K. Parhi (J. VLSI Signal Process., 2002)

Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S. - Francisco Cardells-Tormo; Javier Valls-Coquillat; Vicenc Almenar-Terre (FPL, 2003)

DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems. - José Marín-Roig; Vicente Torres-Carot; Ma José Canet; Asuncion Perez-Pascual; Trinidad Sansaloni; Francisco Cardells-Tormo; Fabian Angarita; Felip Vicedo; Vicenc Almenar-Terre; Javier Valls-Coquillat (FPL, 2003)

Quadrature direct digital frequency synthesizers: area-optimized design map for LUT-based FPGAs. - Francisco Cardells-Tormo; Javier Valls-Coquillat (ISCAS (2), 2003)

Area-optimized implementation of quadrature direct digital frequency synthesizers on LUT-based FPGAs. - Francisco Cardells-Tormo; Javier Valls-Coquillat (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

Efficient FPGA-implementation of two's complement digit-serial/parallel multipliers. - Javier Valls; Eduardo I. Boemo (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

Digit-Serial Complex-Number Multipliers on FPGAs. - T. Sansaloni; Javier Valls; Keshab K. Parhi (J. VLSI Signal Process., 2003)

Power analysis and estimation tool integrated with XPOWER. - Elias Todorovich; Eduardo I. Boemo; Francisco Cardells-Tormo; Javier Valls (FPGA, 2004)

Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2. - Ma José Canet; Felip Vicedo; Vicenc Almenar-Terre; Javier Valls-Coquillat; Eduardo R. de Lima (FPL, 2004)

A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems. - Ma José Canet; Felip Vicedo; Vicenç Almenar; Javier Valls; Eduardo R. de Lima (PIMRC, 2004)

Performance evaluation of fine time synchronizers for WLANs. - Ma José Canet; Ian J. Wassell; Javier Valls; Vicenç Almenar (EUSIPCO, 2005)

Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates. - Fabian Angarita; A. Perez-Pascual; T. Sansaloni; Javier Valls (FPL, 2005)

Statistical Power Estimation for FPGA. - Elias Todorovich; Fabian Angarita; Javier Valls; Eduardo I. Boemo (FPL, 2005)

Design of high performance timing recovery loops for communication applications. - Vicente Torres-Carot; A. Perez-Pascual; T. Sansaloni; Javier Valls (SiPS, 2006)

The use of CORDIC in software defined radios: a tutorial. - Javier Valls; Trinidad Sansaloni; Asuncion Perez-Pascual; Vicente Torres 001; Vicenç Almenar (IEEE Commun. Mag., 2006)

Design of an efficient digital down-converter for a SDR-based DVB-S receiver. - A. Perez-Pascual; T. Sansaloni; Vicente Torres 001; Vicenç Almenar; Javier Valls (ECCTD, 2007)

Improvement of a time synchronization algorithm for IEEE 802.11a/g WLAN standard. - Ma José Canet; Vicenç Almenar; Santiago J. Flores; Javier Valls (EUSIPCO, 2007)

Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms. - Roberto Gutiérrez; Javier Valls (FPL, 2007)

Reduction of power consumption in a Viterbi Decoder for OFDM-WLAN. - Fabian Angarita Preciado; María José Canet; Trinidad Sansaloni Balaguer; Vicenc Almenar-Terre; Javier Valls-Coquillat (ICECS, 2007)

Time Synchronization for the IEEE 802.11a/g WLAN Standard. - María José Canet; Vicenç Almenar; José Marín-Roig; Javier Valls (PIMRC, 2007)

FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices. - Trinidad Sansaloni; Asuncion Perez-Pascual; Vicente Torres-Carot; Vicenç Almenar; José F. Toledo; Javier Valls (IEEE Trans. Educ., 2007)

Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs. - T. Sansaloni; A. Perez-Pascual; Vicente Torres-Carot; Javier Valls (J. VLSI Signal Process., 2007)

64-QAM 4×4 MIMO decoders based on Successive Projection Algorithm. - José Marín-Roig; Vicenç Almenar; Javier Valls; Ma José Canet (ICECS, 2008)

Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN. - Fabian Angarita; Ma José Canet; T. Sansaloni; A. Perez-Pascual; Javier Valls (J. Signal Process. Syst., 2008)

Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder. - Fabian Angarita; Ma José Canet; T. Sansaloni; Javier Valls; Vicenc Almenar-Terre (J. Signal Process. Syst., 2008)

FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic. - Roberto Gutiérrez; Javier Valls; Asuncion Perez-Pascual (FPL, 2009)

Power Consumption Reduction in a Viterbi Decoder for OFDM-WLAN. - Fabian Angarita; Ma José Canet; Trinidad Sansaloni; Vicenç Almenar; Javier Valls (J. Circuits Syst. Comput., 2009)

50 Years of CORDIC: Algorithms, Architectures, and Applications. - Pramod Kumar Meher; Javier Valls; Tso-Bing Juang; K. Sridharan 001; Koushik Maharatna (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications. - Roberto Gutiérrez; Javier Valls (J. Signal Process. Syst., 2009)

Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems. - A. Perez-Pascual; T. Sansaloni; Vicente Torres-Carot; Vicenc Almenar-Terre; Javier Valls (J. Signal Process. Syst., 2009)

Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications. - Vicente Torres-Carot; A. Perez-Pascual; T. Sansaloni; Javier Valls (J. Signal Process. Syst., 2009)

FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques. - Roberto Gutiérrez; Vicente Torres-Carot; Javier Valls-Coquillat (J. Syst. Archit., 2010)

High-Speed RS(255, 239) Decoder Based on LCC Decoding. - Francisco Garcia-Herrero; Javier Valls; Pramod Kumar Meher (Circuits Syst. Signal Process., 2011)

Low Cost Hardware Implementation of Logarithm Approximation. - Roberto Gutiérrez; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2011)

High-throughput FPGA-based emulator for structured LDPC codes. - Fabian Angarita; Vicente Torres-Carot; Asuncion Perez-Pascual; Javier Valls (ICECS, 2012)

Decoder for an enhanced serial generalized bit flipping algorithm. - Francisco Garcia-Herrero; María José Canet; Javier Valls (ICECS, 2012)

Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA. - Vicente Torres-Carot; Asuncion Perez-Pascual; Trinidad Sansaloni; Javier Valls (ICECS, 2012)

Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes. - Francisco Garcia-Herrero; María José Canet; Javier Valls; Mark F. Flanagan (IEEE Commun. Lett., 2012)

Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation. - Fabian Angarita; José Marín-Roig; Vicenç Almenar; Javier Valls (IET Commun., 2012)

FPGA implementation of an OFDM-based WLAN receiver. - María José Canet; Javier Valls; Vicenç Almenar; José Marín-Roig (Microprocess. Microsystems, 2012)

Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method. - Roberto Gutiérrez; Vicente Torres-Carot; Javier Valls (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. - Francisco Garcia-Herrero; María José Canet; Javier Valls; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes. - Fabian Angarita; Trinidad Sansaloni; María José Canet; Javier Valls (J. Signal Process. Syst., 2012)

Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes. - Fabian Angarita; Trinidad Sansaloni; Asuncion Perez-Pascual; Javier Valls (J. Signal Process. Syst., 2012)

Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles. - María José Canet; Vicenc Almenar-Terre; Santiago J. Flores; Javier Valls (J. Signal Process. Syst., 2012)

Low latency T-EMS decoder for non-binary LDPC codes. - Erbao Li; Francisco Garcia-Herrero; David Declercq; Kiran K. Gunnam; Jesus Omar Lacruz; Javier Valls (ACSSC, 2013)

High-speed NB-LDPC decoder for wireless applications. - Francisco Garcia-Herrero; Ma José Canet; Javier Valls (ISPACS, 2013)

Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes. - Francisco Garcia-Herrero; María José Canet; Javier Valls (Circuits Syst. Signal Process., 2013)

A symbol flipping decoder for NB-LDPC relying on multiple votes. - Francisco Garcia-Herrero; David Declercq; Javier Valls (ISTC, 2014)

Reliability-Based Iterative Decoding Algorithm for LDPC Codes With Low Variable-Node Degree. - J. M. Català-Pérez; Francisco Garcia-Herrero; Javier Valls; K. Liu; Shu Lin 001 (IEEE Commun. Lett., 2014)

Non-Binary LDPC Decoder Based on Symbol Flipping with Multiple Votes. - Francisco Garcia-Herrero; David Declercq; Javier Valls (IEEE Commun. Lett., 2014)

Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain. - Guillermo A. Jaquenod; Javier Valls; Javier Siman (Int. J. Reconfigurable Comput., 2014)

Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor. - Fabian Angarita; Javier Valls; Vicenç Almenar; Vicente Torres-Carot (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm. - Francisco Garcia-Herrero; María José Canet; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes. - Francisco Garcia-Herrero; Erbao Li; David Declercq; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 630 Mbps non-binary LDPC decoder for FPGA. - Jesus Omar Lacruz; Francisco Garcia-Herrero; Ma José Canet; Javier Valls; Asuncion Perez-Pascual (ISCAS, 2015)

Low-Complexity Time Synchronization Algorithm for Optical OFDM PON System Using a Directly Modulated DFB Laser. - Julián S. Bruno; Vicenç Almenar; Javier Valls; Juan L. Corral (JOCN, 2015)

One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes. - Jesus Omar Lacruz; Francisco Garcia-Herrero; Javier Valls-Coquillat; David Declercq (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes. - Jesus Omar Lacruz; Francisco Garcia-Herrero; David Declercq; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages. - Jesus Omar Lacruz; Francisco Garcia-Herrero; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2015)

High-Performance NB-LDPC Decoder With Reduction of Message Exchange. - Jesus Omar Lacruz; Francisco Garcia-Herrero; María José Canet; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm. - Jesus Omar Lacruz; Francisco Garcia-Herrero; María José Canet; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Fast- and Low-Complexity atan2(a, b) Approximation [Tips and Tricks]. - Vicente Torres 001; Javier Valls; Richard G. Lyons (IEEE Signal Process. Mag., 2017)

A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number. - Vicente Torres 001; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2017)

High-Throughput One-Channel RS(255, 239) Decoder. - Gabriele Perrone; Javier Valls; Vicente Torres 001; Francisco Miguel Garcia-Herrero (DSD, 2018)

Multidimensional Multiplexing in Multicore Fibre for Hybrid Optical Backhaul provision: The XCORE Approach. - Roberto Llorente; Maria Morant; Julián S. Bruno; Vicenç Almenar; Juan Luis Corral; Jose M. Fuster; Javier Valls (ICTON, 2018)

Soft-decision LCC Decoder Architecture with n=4 for RS(255, 239). - Vicente Torres 001; Javier Valls; María José Canet; Francisco Garcia-Herrero (NEWCAS, 2018)

Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes. - J. M. Català-Pérez; Jesus Omar Lacruz; Francisco Garcia-Herrero; Javier Valls; David Declercq (Circuits Syst. Signal Process., 2019)

Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems. - Gabriele Perrone; Javier Valls; Vicente Torres 001; Francisco Garcia-Herrero (Circuits Syst. Signal Process., 2019)

FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems. - Julián S. Bruno; Vicenç Almenar; Javier Valls (Microprocess. Microsystems, 2019)

A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding. - Javier Valls; Vicente Torres 001; María José Canet; Francisco Miguel Garcia-Herrero (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes. - Javier Valls; Francisco Garcia-Herrero; Nithin Raveendran; Bane Vasic (IEEE Access, 2021)

Layered Decoding of Quantum LDPC Codes. - Julien du Crest; Francisco Garcia-Herrero; Mehdi Mhalla; Valentin Savin; Javier Valls (ISTC, 2023)

Model and Methodology to Characterize Phosphor-Based White LED Visible Light Communication Links. - Pau Salvador; Vicenç Almenar; Juan Luis Corral; Javier Valls; María José Canet (Sensors, 2023)

Hybrid POF-VLC Network Downlink in Indoor Environments. - Pau Salvador; Ma José Canet; Javier Valls; Vicenç Almenar; Juan Luis Corral (VCC, 2024)

Acoustic detection of the effects of prolonged fasting on newly hatched broiler chickens. - Gerardo José Ginovart-Panisello; Ignasi Iriondo; Tesa Panisello Monjo; Silvia Riva; Rodrigo Garcia; Javier Valls; Rosa Maria Alsina Pages (Comput. Electron. Agric., 2024)

Check-Agnosia based Post-Processor for Message-Passing Decoding of Quantum LDPC Codes. - Julien du Crest; Francisco Garcia-Herrero; Mehdi Mhalla; Valentin Savin; Javier Valls (Quantum, 2024)