Two-level hierarchical register file organization for VLIW processors. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (MICRO, 2000)

Improved spill code generation for software pipelined loops. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (PLDI, 2000)

MIRS: Modulo Scheduling with Integrated Register Spilling. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (LCPC, 2001)

Modulo scheduling with integrated register spilling for clustered VLIW architectures. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (MICRO, 2001)

Hierarchical Clustered Register File Organization for VLIW Processors. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (IPDPS, 2003)

Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (ISHPC, 2003)

Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (SAMOS, 2004)

High-performance and low-power VLIW cores for numerical computations. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (Int. J. High Perform. Comput. Netw., 2004)

Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (Int. J. Parallel Program., 2004)

Register Constrained Modulo Scheduling. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (IEEE Trans. Parallel Distributed Syst., 2004)

Power-efficient VLIW design using clustering and widening. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (Int. J. Embed. Syst., 2008)