Computing the correct Increment of Induction Pointers with application to loop unrolling. - Yosi Ben-Asher; Jawad Haj-Yihia (J. Syst. Archit., 2010)

Compiler-Directed Power Management for Superscalars. - Jawad Haj-Yihia; Yosi Ben-Asher; Efraim Rotem; Ahmad Yasin; Ran Ginosar (ACM Trans. Archit. Code Optim., 2014)

DOEE: dynamic optimization framework for better energy efficiency. - Jawad Haj-Yihia; Ahmad Yasin; Yosi Ben-Asher (SpringSim (HPS), 2015)

Fine-Grain Power Breakdown of Modern Out-of-Order Cores and Its Implications on Skylake-Based Systems. - Jawad Haj-Yihia; Ahmad Yasin; Yosi Ben-Asher; Avi Mendelson (ACM Trans. Archit. Code Optim., 2016)

Survey of secure processors. - Suman Sau; Jawad Haj-Yahya; Ming Ming Wong; Kwok-Yan Lam; Anupam Chattopadhyay (SAMOS, 2017)

A Comprehensive Performance Analysis of Hardware Implementations of CAESAR Candidates. - Sachin Kumar; Jawad Haj-Yihia; Mustafa Khairallah; Anupam Chattopadhyay (IACR Cryptol. ePrint Arch., 2017)

Energy, power and performance optimizations using compiler and hardware aided tools. - Jawad Haj-Yihia (2017)

SMARTS: secure memory assurance of RISC-V trusted SoC. - Ming Ming Wong; Jawad Haj-Yahya; Anupam Chattopadhyay (HASP@ISCA, 2018)

Efficient Hardware Accelerator for NORX Authenticated Encryption. - Sachin Kumar; Jawad Haj-Yahya; Anupam Chattopadhyay (ISCAS, 2018)

A New High Throughput and Area Efficient SHA-3 Implementation. - Ming Ming Wong; Jawad Haj-Yahya; Suman Sau; Anupam Chattopadhyay (ISCAS, 2018)

Anti-forensic = Suspicious: Detection of Stealthy Malware that Hides Its Network Traffic. - Mayank Agarwal; Rami Puzis; Jawad Haj-Yahya; Polina Zilberman; Yuval Elovici (SEC, 2018)

Software Static Energy Modeling for Modern Processors. - Jawad Haj-Yihia; Yosi Ben-Asher (Int. J. Parallel Program., 2018)

A Comprehensive Evaluation of Power Delivery Schemes for Modern Microprocessors. - Jawad Haj-Yahya; Efraim Rotem; Avi Mendelson; Anupam Chattopadhyay (ISQED, 2019)

Lightweight Secure-Boot Architecture for RISC-V System-on-Chip. - Jawad Haj-Yahya; Ming Ming Wong; Vikramkumar Pudi; Shivam Bhasin; Anupam Chattopadhyay (ISQED, 2019)

ITUS: A Secure RISC-V System-on-Chip. - Vinay B. Y. Kumar; Anupam Chattopadhyay; Jawad Haj-Yahya; Avi Mendelson (SoCC, 2019)

SoCINT: Resilient System-on-Chip via Dynamic Intrusion Detection. - Amr Sayed-Ahmed; Jawad Haj-Yahya; Anupam Chattopadhyay (VLSID, 2019)

Techniques for Reducing the Connected-Standby Energy Consumption of Mobile Devices. - Jawad Haj-Yahya; Yanos Sazeides; Mohammed Alser; Efraim Rotem; Onur Mutlu (HPCA, 2020)

SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors. - Jawad Haj-Yahya; Mohammed Alser; Jeremie S. Kim; Abdullah Giray Yaglikçi; Nandita Vijaykumar; Efraim Rotem; Onur Mutlu (ISCA, 2020)

FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors. - Jawad Haj-Yahya; Mohammed Alser; Jeremie S. Kim; Lois Orosa 001; Efraim Rotem; Avi Mendelson; Anupam Chattopadhyay; Onur Mutlu (MICRO, 2020)

Towards Designing a Secure RISC-V System-on-Chip: ITUS. - Vinay B. Y. Kumar; Suman Deb; Naina Gupta 001; Shivam Bhasin; Jawad Haj-Yahya; Anupam Chattopadhyay; Avi Mendelson (J. Hardw. Syst. Secur., 2020)

A Metric-Guided Method for Discovering Impactful Features and Architectural Insights for Skylake-Based Processors. - Ahmad Yasin; Jawad Haj-Yahya; Yosi Ben-Asher; Avi Mendelson (ACM Trans. Archit. Code Optim., 2020)

IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors. - Jawad Haj-Yahya; Lois Orosa 001; Jeremie S. Kim; Juan Gómez-Luna; Abdullah Giray Yaglikçi; Mohammed Alser; Ivan Puddu; Onur Mutlu (ISCA, 2021)

BurstLink: Techniques for Energy-Efficient Video Display for Conventional and Virtual Reality Systems. - Jawad Haj-Yahya; Jisung Park 001; Rahul Bera; Juan Gómez-Luna; Efraim Rotem; Taha Shahroodi; Jeremie S. Kim; Onur Mutlu (MICRO, 2021)

BurstLink: Techniques for Energy-Efficient Conventional and Virtual Reality Video Display. - Jawad Haj-Yahya; Jisung Park 001; Rahul Bera; Juan Gómez-Luna; Efraim Rotem; Taha Shahroodi; Jeremie S. Kim; Onur Mutlu (CoRR, 2021)

DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors. - Jawad Haj-Yahya; Jeremie S. Kim; Abdullah Giray Yaglikçi; Jisung Park 001; Efraim Rotem; Yanos Sazeides; Onur Mutlu (HPCA, 2022)

AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers. - Georgia Antoniou; Haris Volos 001; Davide B. Bartolini; Tom Rollet; Yiannakis Sazeides; Jawad Haj-Yahya (MICRO, 2022)

AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications. - Jawad Haj-Yahya; Haris Volos 001; Davide B. Bartolini; Georgia Antoniou; Jeremie S. Kim; Zhe Wang 023; Kleovoulos Kalaitzidis; Tom Rollet; Zhirui Chen; Ye Geng; Onur Mutlu; Yiannakis Sazeides (MICRO, 2022)

Decoding Attack Behaviors by Analyzing Patterns in Instruction-Based Attacks using gem5. - Muhammad Awais; Maria Mushtaq; Lirida Naviner; Florent Bruguier; Jawad Haj-Yahya; Pascal Benoit (RSP, 2024)

Agile C-states: A Core C-state Architecture for Latency Critical Applications Optimizing both Transition and Cold-Start Latency. - Georgia Antoniou; Davide B. Bartolini; Haris Volos 001; Marios Kleanthous; Zhe Wang 023; Kleovoulos Kalaitzidis; Tom Rollet; Ziwei Li; Onur Mutlu; Yiannakis Sazeides; Jawad Haj-Yahya (ACM Trans. Archit. Code Optim., 2024)