Jawad Haj-Yahya

Orcid: 0000-0003-2911-0329

According to our database1, Jawad Haj-Yahya authored at least 27 papers between 2010 and 2022.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021
BurstLink: Techniques for Energy-Efficient Conventional and Virtual Reality Video Display.
CoRR, 2021

BurstLink: Techniques for Energy-Efficient Video Display for Conventional and Virtual Reality Systems.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
A Metric-Guided Method for Discovering Impactful Features and Architectural Insights for Skylake-Based Processors.
ACM Trans. Archit. Code Optim., 2020

Towards Designing a Secure RISC-V System-on-Chip: ITUS.
J. Hardw. Syst. Secur., 2020

FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Techniques for Reducing the Connected-Standby Energy Consumption of Mobile Devices.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019
SoCINT: Resilient System-on-Chip via Dynamic Intrusion Detection.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

ITUS: A Secure RISC-V System-on-Chip.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Lightweight Secure-Boot Architecture for RISC-V System-on-Chip.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

A Comprehensive Evaluation of Power Delivery Schemes for Modern Microprocessors.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

2018
Software Static Energy Modeling for Modern Processors.
Int. J. Parallel Program., 2018

Anti-forensic = Suspicious: Detection of Stealthy Malware that Hides Its Network Traffic.
Proceedings of the ICT Systems Security and Privacy Protection, 2018

A New High Throughput and Area Efficient SHA-3 Implementation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Efficient Hardware Accelerator for NORX Authenticated Encryption.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

SMARTS: secure memory assurance of RISC-V trusted SoC.
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018

2017
Energy, power and performance optimizations using compiler and hardware aided tools.
PhD thesis, 2017

A Comprehensive Performance Analysis of Hardware Implementations of CAESAR Candidates.
IACR Cryptol. ePrint Arch., 2017

Survey of secure processors.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

2016
Fine-Grain Power Breakdown of Modern Out-of-Order Cores and Its Implications on Skylake-Based Systems.
ACM Trans. Archit. Code Optim., 2016

2015
DOEE: dynamic optimization framework for better energy efficiency.
Proceedings of the Symposium on High Performance Computing, 2015

2014
Compiler-Directed Power Management for Superscalars.
ACM Trans. Archit. Code Optim., 2014

2010
Computing the correct Increment of Induction Pointers with application to loop unrolling.
J. Syst. Archit., 2010


  Loading...