Probabilistic Design Verification. - Jawahar Jain; James R. Bitner; Donald S. Fussell; Jacob A. Abraham (ICCAD, 1991)

Probabilistic Verification of Boolean Functions. - Jawahar Jain; Jacob A. Abraham; James R. Bitner; Donald S. Fussell (Formal Methods Syst. Des., 1992)

Efficient Algorithmic Circuit Verification Using Indexed BDDs. - James R. Bitner; Jawahar Jain; Magdy S. Abadir; Jacob A. Abraham; Donald S. Fussell (FTCS, 1994)

A new scheme to compute variable orders for binary decision diagrams. - Jawahar Jain; James R. Bitner; Dinos Moundanos; Jacob A. Abraham; Donald S. Fussell (Great Lakes Symposium on VLSI, 1994)

Functional learning: a new approach to learning in digital circuits. - Rajarshi Mukherjee; Jawahar Jain; Dhiraj K. Pradhan (VTS, 1994)

Advanced Verification Techniques Based on Learning. - Jawahar Jain; Rajarshi Mukherjee; Masahiro Fujita (DAC, 1995)

VERIFUL: VERIfication using FUnctional Learning. - Rajarshi Mukherjee; Jawahar Jain; Masahiro Fujita (ED&TC, 1995)

Efficient variable ordering and partial representation algorithm. - Jawahar Jain; Dinos Moundanos; James R. Bitner; Jacob A. Abraham; Donald S. Fussell; Don E. Ross (VLSI Design, 1995)

Decomposition Techniques for Efficient ROBDD Construction. - Jawahar Jain; Amit Narayan; C. Coelho 001; Sunil P. Khatri; Alberto L. Sangiovanni-Vincentelli; Robert K. Brayton; Masahiro Fujita (FMCAD, 1996)

Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. - Amit Narayan; Jawahar Jain; Masahiro Fujita; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1996)

On More Efficient Combinational ATPG Using Functional Learning. - Rajarshi Mukherjee; Jawahar Jain; Masahiro Fujita; Jacob A. Abraham; Donald S. Fussell (VLSI Design, 1996)

A study of composition schemes for mixed apply/compose based construction of ROBDDs. - Amit Narayan; Sunil P. Khatri; Jawahar Jain; Masahiro Fujita; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (VLSI Design, 1996)

Reachability analysis using partitioned-ROBDDs. - Amit Narayan; Adrian J. Isles; Jawahar Jain; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1997)

A Survey of Techniques for Formal Verification of Combinational Circuits. - Jawahar Jain; Amit Narayan; Masahiro Fujita; Alberto L. Sangiovanni-Vincentelli (ICCD, 1997)

Formal Verification of Combinational Circuit. - Jawahar Jain; Amit Narayan; Masahiro Fujita; Alberto L. Sangiovanni-Vincentelli (VLSI Design, 1997)

Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions. - Jawahar Jain; James R. Bitner; Magdy S. Abadir; Jacob A. Abraham; Donald S. Fussell (IEEE Trans. Computers, 1997)

Sampling schemes for computing OBDD variable orderings. - Jawahar Jain; William Adams; Masahiro Fujita (ICCAD, 1998)

Multiple Error Diagnosis Based on Xlists. - Vamsi Boppana; Rajarshi Mukherjee; Jawahar Jain; Masahiro Fujita; Pradeep Bollineni (DAC, 1999)

Efficient Scheduling Techniques for ROBDD Construction. - Rajeev Murgai; Jawahar Jain; Masahiro Fujita (VLSI Design, 1999)

An efficient filter-based approach for combinational verification. - Rajarshi Mukherjee; Jawahar Jain; Koichiro Takayama; Masahiro Fujita; Jacob A. Abraham; Donald S. Fussell (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Automatic partitioning for efficient combinatorial verification. - Rajarshi Mukherjee; Jawahar Jain; Koichiro Takayama; Masahiro Fujita (ASP-DAC, 2000)

Analysis of composition complexity and how to obtain smaller canonical graphs. - Jawahar Jain; K. Mohanram; Dinos Moundanos; Ingo Wegener; Yuan Lu 004 (DAC, 2000)

Efficient variable ordering using aBDD based sampling. - Yuan Lu 004; Jawahar Jain; Edmund M. Clarke; Masahiro Fujita (DAC, 2000)

Hierarchical Error Diagnosis Targeting RTL Circuits. - Vamsi Boppana; Indradeep Ghosh; Rajarshi Mukherjee; Jawahar Jain; Masahiro Fujita (VLSI Design, 2000)

Testing, Verification, and Diagnosis in the Presence of Unknowns. - Ankur Jain; Vamsi Boppana; Rajarshi Mukherjee; Jawahar Jain; Masahiro Fujita; Michael S. Hsiao (VTS, 2000)

Practical use of sequential ATPG for model checking: going the extra mile does pay off. - Michael S. Hsiao; Jawahar Jain (HLDVT, 2001)

A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs. - Jawahar Jain; Ingo Wegener; Masahiro Fujita (IEEE Trans. Computers, 2001)

Improving Sequential ATPG Using SAT Methods. - Mukul R. Prasad; Michael S. Hsiao; Jawahar Jain (IWLS, 2002)

Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. - Rajarshi Mukherjee; Jawahar Jain; Koichiro Takayama; Jacob A. Abraham; Donald S. Fussell; Masahiro Fujita (Formal Methods Syst. Des., 2002)

Improved Symbolic Verification Using Partitioning Techniques. - Subramanian K. Iyer; Debashis Sahoo; Christian Stangier; Amit Narayan; Jawahar Jain (CHARME, 2003)

Solving the latch mapping problem in an industrial setting. - Kelvin Ng; Mukul R. Prasad; Rajarshi Mukherjee; Jawahar Jain (DAC, 2003)

A Partitioning Methodology for BDD-Based Verification. - Debashis Sahoo; Subramanian K. Iyer; Jawahar Jain; Christian Stangier; Amit Narayan; David L. Dill; E. Allen Emerson (FMCAD, 2004)

Can SAT be used to Improve Sequential ATPG Methods? - Mukul R. Prasad; Michael S. Hsiao; Jawahar Jain (VLSI Design, 2004)

Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes. - Subramanian K. Iyer; Jawahar Jain; Debashis Sahoo; Takeshi Shimizu (Asian Test Symposium, 2005)

A New Reachability Algorithm for Symmetric Multi-processor Architecture. - Debashis Sahoo; Jawahar Jain; Subramanian K. Iyer; David L. Dill (ATVA, 2005)

Error Detection Using BMC in a Parallel Environment. - Subramanian K. Iyer; Jawahar Jain; Mukul R. Prasad; Debashis Sahoo; Thomas Sidle (CHARME, 2005)

Predictive Reachability Using a Sample-Based Approach. - Debashis Sahoo; Jawahar Jain; Subramanian K. Iyer; David L. Dill; E. Allen Emerson (CHARME, 2005)

Multi-threaded reachability. - Debashis Sahoo; Jawahar Jain; Subramanian K. Iyer; David L. Dill; E. Allen Emerson (DAC, 2005)

Under-approximation Heuristics for Grid-based Bounded Model Checking. - Subramanian K. Iyer; Jawahar Jain; Debashis Sahoo; E. Allen Emerson (PDMC@ICALP, 2005)

Disjunctive Transition Relation Decomposition for Efficient Reachability Analysis. - Stergios Stergiou; Jawahar Jain (HLDVT, 2006)

On partitioning and symbolic model checking. - Subramanian K. Iyer; Debashis Sahoo; E. Allen Emerson; Jawahar Jain (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Optimizing routing tables on systems-on-chip with Content-Addressable Memories. - Stergios Stergiou; Jawahar Jain (SoC, 2008)

Dynamically resizable binary decision diagrams. - Stergios Stergiou; Jawahar Jain (ACM Great Lakes Symposium on VLSI, 2010)

Optimizing BDDs for time-series dataset manipulation. - Stergios Stergiou; Jawahar Jain (DATE, 2013)

Comparing stress markers across various cohorts in a mobile setting. - Shreyans Gandhi; Jawahar Jain; Maryam Shojaei Baghini; Soumyo Mukherji (EMBC, 2013)