A Triple-Mode Sigma-Delta Modulator Design for Wireless Standards. - Babita R. Jose; P. Mythili; Jawar Singh; Jimson Mathew (ICIT, 2007)

Single Event Upset Detection and Correction. - Jawar Singh; Jimson Mathew; Mohammad Hosseinabady; Dhiraj K. Pradhan (ICIT, 2007)

Fault Tolerant Reversible Finite Field Arithmetic Circuits. - Jimson Mathew; Jawar Singh; Anas Abu Taleb; Dhiraj K. Pradhan (IOLTS, 2008)

Fault tolerant bit parallel finite field multipliers using LDPC codes. - Jimson Mathew; Jawar Singh; Abusaleh M. Jabir; Mohammad Hosseinabady; Dhiraj K. Pradhan (ISCAS, 2008)

A nano-CMOS process variation induced read failure tolerant SRAM cell. - Jawar Singh; Jimson Mathew; Saraju P. Mohanty; Dhiraj K. Pradhan (ISCAS, 2008)

A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. - Jawar Singh; Jimson Mathew; Dhiraj K. Pradhan; Saraju P. Mohanty (SoCC, 2008)

Failure analysis for ultra low power nano-CMOS SRAM under process variations. - Jawar Singh; Jimson Mathew; Dhiraj K. Pradhan; Saraju P. Mohanty (SoCC, 2008)

Pseudo parallel architecture for AES with error correction. - Yi Xin Su; Jimson Mathew; Jawar Singh; Dhiraj K. Pradhan (SoCC, 2008)

A single ended 6T SRAM cell design for ultra-low-voltage applications. - Jawar Singh; Dhiraj K. Pradhan; Simon Hollis; Saraju P. Mohanty (IEICE Electron. Express, 2008)

Single ended 6T SRAM with isolated read-port for low-power embedded systems. - Jawar Singh; Dhiraj K. Pradhan; Simon Hollis; Saraju P. Mohanty; Jimson Mathew (DATE, 2009)

Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. - Jawar Singh; Jimson Mathew; Saraju P. Mohanty; Dhiraj K. Pradhan (VLSI Design, 2009)

Robust power aware SRAM bitcell designs. - Jawar Singh (2009)

A novel si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications. - Jawar Singh; Krishnan Ramakrishnan; Saurabh Mookerjea; Suman Datta; Narayanan Vijaykrishnan; Dhiraj K. Pradhan (ASP-DAC, 2010)

Investigating the impact of NBTI on different power saving cache strategies. - Andrew J. Ricketts; Jawar Singh; Krishnan Ramakrishnan; Narayanan Vijaykrishnan; Dhiraj K. Pradhan (DATE, 2010)

A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead. - Jawar Singh; Dilip S. Aswar; Saraju P. Mohanty; Dhiraj K. Pradhan (ISQED, 2010)

Process variation tolerant 9T SRAM bitcell design. - G. K. Reddy; Kapil Jainwal; Jawar Singh; Saraju P. Mohanty (ISQED, 2012)

Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM. - Saraju P. Mohanty; Jawar Singh; Elias Kougianos; Dhiraj K. Pradhan (Integr., 2012)

Dual sided doped memristor and it's mathematical modelling. - Anup Shrivastava; Jawar Singh (ICECS, 2013)

An Efficient RF Energy Harvester with Tuned Matching Circuit. - Sachin Agrawal; Sunil Kumar Pandey; Jawar Singh; Pravin Neminath Kondekar (VDAT, 2013)

A highly reliable NBTI Resilient 6T SRAM cell. - Jawar Singh; Narayanan Vijaykrishnan (Microelectron. Reliab., 2013)

Realization of efficient RF energy harvesting circuits employing different matching technique. - Sachin Agrawal; Sunil Kumar Pandey; Jawar Singh; Manoj Singh Parihar (ISQED, 2014)

Dual-sided doped memristor and it's SPICE modelling for improved electrical properties. - Anup Shrivastava; Jawar Singh (ISQED, 2014)

Linearly separable pattern classification using memristive crossbar circuits. - Komal Singh; Chitrakant Sahu; Jawar Singh (ISQED, 2014)

Modeling and simulation of variable thickness based stepped MEMS cantilever designs for biosensing and pull-in voltage optimization. - Deep Kishore Parsediya; Jawar Singh; Pavan Kumar Kankar (VDAT, 2014)

Extended Base Schottky-Collector Bipolar Charge Plasma Transistor. - Lokesh Kumar Bramhane; Jawar Singh (iNIS, 2015)

Performance Enhancement of Dopingless Tunnel-FET Based on Ge-Source with High-k. - Kanchan Cecil; Jawar Singh (iNIS, 2015)

A low power and high gain CMOS LNA for UWB applications in 90 nm CMOS process. - Sunil Kumar Pandey; Jawar Singh (Microelectron. J., 2015)

Memristor Crossbar-Based Pattern Recognition Circuit Using Perceptron Learning Rule. - Muhammad Khalid; Jawar Singh (iNIS, 2016)

Proposal of Heterogate Technique for Performance Enhancement of DM-TFET. - Chaitanya Maradana; Jawar Singh (iNIS, 2016)

Compact Behavioral Modeling and Time Dependent Performance Degradation Analysis of Junction and Doping Free Transistors. - Meena Panchore; Jawar Singh; Saraju P. Mohanty; Elias Kougianos (iNIS, 2016)

Secure Multi-key Generation Using Ring Oscillator Based Physical Unclonable Function. - Venkata P. Yanambaka; Saraju P. Mohanty; Elias Kougianos; Jawar Singh (iNIS, 2016)

SiGe Source Charge Plasma TFET for Biosensing Applications. - Nawaz Shafi; Chitrakant Sahu; C. Periasamy; Jawar Singh (iNIS, 2017)

Dopingless Transistor Based Hybrid Oscillator Arbiter Physical Unclonable Function. - Venkata P. Yanambaka; Saraju P. Mohanty; Elias Kougianos; Prabha Sundaravadivel; Jawar Singh (ISVLSI, 2017)

Reconfigurable Robust Hybrid Oscillator Arbiter PUF for IoT Security Based on DL-FET. - Venkata P. Yanambaka; Saraju P. Mohanty; Elias Kougianos; Prabha Sundaravadivel; Jawar Singh (ISVLSI, 2017)

Analog/RF Performance Investigation of Dopingless FET for Ultra-Low Power Applications. - Ankit Sirohi; Chitrakant Sahu; Jawar Singh (IEEE Access, 2019)

Ultra-Low Energy and High Speed LIF Neuron using Silicon Bipolar Impact Ionization MOSFET for Spiking Neural Networks. - Alok Kumar Kamal; Jawar Singh (CoRR, 2019)

Improvement in Retention Time of Capacitorless DRAM with Access Transistor. - Md. Hasan Raza Ansari; Jawar Singh (CoRR, 2019)

Blockchain-based Interoperable Healthcare using Zero-Knowledge Proofs and Proxy Re-Encryption. - Bhavye Sharma; Raju Halder; Jawar Singh (COMSNETS, 2020)

In-memory Implementation of On-chip Trainable and Scalable ANN for AI/ML Applications. - Abhash Kumar; Jawar Singh; Sai Manohar Beeraka; Bharat Gupta (CoRR, 2020)

A Framework for the Automation of Platform Validation for Use Cases of Wi-Fi. - Kota Nikhileswar; Sudhir Kumar 002; Jawar Singh; Dharmendra Muthuswamy (ICIT, 2022)

A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold Contact. - Ankit Sirohi; Jawar Singh (VLSI-SoC, 2023)

Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison. - V. Bharath Sreenivasulu; Aruna Kumari Neelam; Sekhar Reddy Kola; Jawar Singh; Yiming Li 005 (IEEE Access, 2023)

Design and analysis of DDoS mitigating network architecture. - Swati; Sangita Roy; Jawar Singh; Jimson Mathew (Int. J. Inf. Sec., 2023)

An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI/ML Applications. - Abhash Kumar; Sai Manohar Beeraka; Jawar Singh; Bharat Gupta (Circuits Syst. Signal Process., 2023)

Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications. - V. Bharath Sreenivasulu; Aruna Kumari Neelam; Asisa Kumar Panigrahy; Lokesh Vakkalakula; Jawar Singh; Shiv Govind Singh (IEEE Access, 2024)

Investigation of Silicon Aging Effects in Dopingless PUF for Reliable Security Solution. - Meena Panchore; Chithraja Rajan; Jawar Singh (J. Electron. Test., 2024)