TRIBuTETM Board and Platform Test Methodology: Intel's Next-Generation Test and Validation Methodology for Platforms. - Jay J. Nejedlo (ITC, 2003)

IBISTTM (Interconnect Built-in Self-Test) Architecture and Methodology for PCI Express: Intel?s Next-Generation Test and Validation Methodology for Performance IO. - Jay J. Nejedlo (ITC, 2003)

Functional Test Coverage Effectiveness on the Decline. - Jay J. Nejedlo (ITC, 2004)

Intel® IBIST, the full vision realized. - Jay J. Nejedlo; Rahul Khanna (ITC, 2009)

Short-Range, Wireless Interconnect within a Computing Chassis: Design Challenges. - Patrick Yin Chiang; Sirikarn Woracheewan; Changhui Hu 003; Lei Guo; Rahul Khanna; Jay J. Nejedlo; Huaping Liu 002 (IEEE Des. Test Comput., 2010)

A 90 nm-CMOS, 500 Mbps, 3-5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization. - Changhui Hu 003; Rahul Khanna; Jay J. Nejedlo; Kangmin Hu; Huaping Liu 002; Patrick Yin Chiang (IEEE J. Solid State Circuits, 2011)