Achieving High Test Quality with Reduced Pin Count Testing. - Jay Jahangiri; Nilanjan Mukherjee 001; Wu-Tung Cheng; Subramanian Mahadevan; Ron Press (Asian Test Symposium, 2005)

Meeting Nanometer DPM Requirements Through DFT. - Jay Jahangiri; David Abercrombie (ISQED, 2005)

Value-Added Defect Testing Techniques. - Jay Jahangiri; David Abercrombie (IEEE Des. Test Comput., 2005)

The Demand and Practical Approach for 100x Test Compression. - Ron Press; Jay Jahangiri (VLSI-SoC, 2006)

Silicon Evaluation of Static Alternative Fault Models. - Chris Schuermyer; Jewel Pangilinan; Jay Jahangiri; Martin Keim; Janusz Rajski; Brady Benware (VTS, 2007)

Test Compression Improvement with EDT Channel Sharing in SoC Designs. - Yu Huang 005; Mark Kassab; Jay Jahangiri; Janusz Rajski; Wu-Tung Cheng; Dongkwan Han; Jihye Kim 002; Kun Young Chung (NATW, 2014)