A Hierarchical Register Optimization Algorithm for Behavioral Synthesis. - Srinivas Katkoori; Ranga Vemuri; Jay Roy (VLSI Design, 1996)

Synchronous Controller Models for Synthesis from Communicating VHDL Processes. - Naren Narasimhan; Ranga Vemuri; Jay Roy (VLSI Design, 1996)

An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications. - Ranga Vemuri; Srinivas Katkoori; Meenakshi Kaul; Jay Roy (ACM Trans. Design Autom. Electr. Syst., 2002)