Optimizations for a Highly Cost-Efficient Programmable Logic Architecture. - Kerry Veenstra; Bruce Pedersen; Jay Schleicher; Chiakang Sung (FPGA, 1998)

A next generation architecture optimized for high density system level integration. - Richard Cliff; Srinivas Reddy; Cameron McClintock; David Jefferslon; Christopher Lane; Ketan Zaveri; Manuel Mejia; Andy Lee; Ninh Ngo; Risa Altaf; Bruce Pedersen; Frank Heile; et al. (CICC, 1999)

Interconnect enhancements for a high-speed PLD architecture. - Michael D. Hutton; Vinson Chan; Peter Kazarian; Victor Maruri; Tony Ngai; Jim Park; Rakesh H. Patel; Bruce Pedersen; Jay Schleicher; Sergey Y. Shumarayev (FPGA, 2002)

Improving FPGA Performance and Area Using an Adaptive Logic Module. - Michael D. Hutton; Jay Schleicher; David M. Lewis; Bruce Pedersen; Richard Yuan; Sinan Kaptanoglu; Gregg Baeckler; Boris Ratchev; Ketan Padalia; Mark Bourgeault; Andy Lee; Henry Kim; et al. (FPL, 2004)

The Stratix II logic and routing architecture. - David M. Lewis; Elias Ahmed; Gregg Baeckler; Vaughn Betz; Mark Bourgeault; David Cashman; David R. Galloway; Mike Hutton; Christopher Lane; Andy Lee; Paul Leventis; Sandy Marquardt; et al. (FPGA, 2005)

A methodology for FPGA to structured-ASIC synthesis and verification. - Michael D. Hutton; Richard Yuan; Jay Schleicher; Gregg Baeckler; Sammy Cheung; Kar Keng Chua; Hee Kong Phoo (DATE Designers' Forum, 2006)

Equivalence Verification of FPGA and Structured ASIC Implementations. - Joachim Pistorius; Mike Hutton; Jay Schleicher; Mihail Iotov; Enoch Julias; Kumara Tharmalingam (FPL, 2007)