Statistical guarantees of performance for MIMO designs. - Jayanand Asok Kumar; Shobha Vasudevan (DSN, 2010)

Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs. - Jayanand Asok Kumar; Shobha Vasudevan (QEST, 2010)

Scaling probabilistic timing verification of hardware using abstractions in design source code. - Jayanand Asok Kumar; Lingyi Liu; Shobha Vasudevan (FMCAD, 2011)

Variation-Conscious Formal Timing Verification in RTL. - Jayanand Asok Kumar; Shobha Vasudevan (VLSI Design, 2011)

Verifying dynamic power management schemes using statistical model checking. - Jayanand Asok Kumar; Shobha Vasudevan (ASP-DAC, 2012)

Goal-oriented stimulus generation for analog circuits. - Seyed Nematollah Ahmadyan; Jayanand Asok Kumar; Shobha Vasudevan (DAC, 2012)

Early prediction of NBTI effects using RTL source code analysis. - Jayanand Asok Kumar; Kenneth M. Butler; Heesoo Kim; Shobha Vasudevan (DAC, 2012)

Formal Performance Analysis for Faulty MIMO Hardware. - Jayanand Asok Kumar; Shobha Vasudevan (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Statistical guarantees of performance for RTL designs - Jayanand Asok Kumar (2012)

Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm. - Seyed Nematollah Ahmadyan; Jayanand Asok Kumar; Shobha Vasudevan (DATE, 2013)

Formal Probabilistic Timing Verification in RTL. - Jayanand Asok Kumar; Shobha Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions. - Jayanand Asok Kumar; Seyed Nematollah Ahmadyan; Shobha Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)