Improving Witness Search Using Orders on States. - Robert W. Sumners; Jayanta Bhadra; Jacob A. Abraham (ICCD, 1999)

A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPCTM microprocessor. - Jayanta Bhadra; Magdy S. Abadir; Jacob A. Abraham (CICC, 2000)

Automatic Validation Test Generation Using Extracted Control Models. - Robert W. Sumners; Jayanta Bhadra; Jacob A. Abraham (VLSI Design, 2000)

Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation. - Jayanta Bhadra; Andrew K. Martin; Jacob A. Abraham; Magdy S. Abadir (CHARME, 2001)

Full chip false timing path identification: applications to the PowerPCTM microprocessors. - Jing Zeng; Magdy S. Abadir; Jayanta Bhadra; Jacob A. Abraham (DATE, 2001)

A language formalism for verification of PowerPCTM custom memories using compositions of abstract specifications. - Jayanta Bhadra; Andrew K. Martin; Jacob A. Abraham; Magdy S. Abadir (HLDVT, 2001)

Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits. - Jayanta Bhadra; Narayanan Krishnamurthy (ITC, 2002)

Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? - Narayanan Krishnamurthy; Jayanta Bhadra; Magdy S. Abadir; Jacob A. Abraham (VTS, 2002)

Program Slicing for Hierarchical Test Generation. - Vivekananda M. Vedula; Jacob A. Abraham; Jayanta Bhadra (VTS, 2002)

A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. - Jayanta Bhadra; Narayanan Krishnamurthy; Magdy S. Abadir (MTV, 2003)

Model Checking of Security Protocols with Pre-configuration. - Kyoil Kim; Jacob A. Abraham; Jayanta Bhadra (WISA, 2003)

A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages. - Vivekananda M. Vedula; Jacob A. Abraham; Jayanta Bhadra; Raghuram S. Tupuri (J. Electron. Test., 2003)

Formal Verification of a System-on-Chip Using Computation Slicing. - Alper Sen 001; Vijay K. Garg; Jacob A. Abraham; Jayanta Bhadra (ITC, 2004)

Towards The Complete Elimination of Gate/Switch Level Simulations. - Narayanan Krishnamurthy; Jayanta Bhadra; Magdy S. Abadir; Jacob A. Abraham (VLSI Design, 2004)

Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation. - Jayanta Bhadra; Narayanan Krishnamurthy; Magdy S. Abadir (IEEE Des. Test Comput., 2004)

Establishing latch correspondence for embedded circuits of PowerPC microprocessors. - Himyanshu Anand; Jayanta Bhadra; Alper Sen 001; Magdy S. Abadir; Kenneth G. Davis (HLDVT, 2005)

Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. - Jayanta Bhadra; Magdy S. Abadir; David Burgess; Ekaterina Trofimova (MTV, 2005)

A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor. - Jayanta Bhadra; Andrew K. Martin; Jacob A. Abraham (Formal Methods Syst. Des., 2005)

Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. - Heon-Mo Koo; Prabhat Mishra 001; Jayanta Bhadra; Magdy S. Abadir (MTV, 2006)

A Trace-Driven Validation Methodology for Multi-Processor SOCS. - Jayanta Bhadra; Ekaterina Trofimova; Leonard J. Giordano; Magdy S. Abadir (SoCC, 2006)

A Mechanized Refinement Framework for Analysis of Custom Memories. - Sandip Ray; Jayanta Bhadra (FMCAD, 2007)

An incremental learning framework for estimating signal controllability in unit-level verification. - Charles H.-P. Wen; Li-C. Wang; Jayanta Bhadra (ICCAD, 2007)

Enhancing signal controllability in functional test-benches through automatic constraint extraction. - Onur Guzey; Li-C. Wang; Jayanta Bhadra (ITC, 2007)

Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. - Jayanta Bhadra; Magdy S. Abadir; Li-C. Wang (IEEE Des. Test Comput., 2007)

A Survey of Hybrid Techniques for Functional Verification. - Jayanta Bhadra; Magdy S. Abadir; Li-C. Wang; Sandip Ray (IEEE Des. Test Comput., 2007)

Validating Power ArchitectureTM Technology-Based MPSoCs Through Executable Specifications. - Jayanta Bhadra; Ekaterina Trofimova; Magdy S. Abadir (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Accelerating multi-party scheduling for transaction-level modeling. - Di Wang; Vyas Venkataraman; Zhen Wang 001; Wei Qin; Hangsheng Wang; Mrinal Bose; Jayanta Bhadra (ACM Great Lakes Symposium on VLSI, 2009)

On soft error rate analysis of scaled CMOS designs - A statistical perspective. - Huan-Kai Peng; Charles H.-P. Wen; Jayanta Bhadra (ICCAD, 2009)

An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs. - Mrinal Bose; Prashant Naphade; Jayanta Bhadra; Hillel Miller (ISQED, 2009)

Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models. - Vyas Venkataraman; Di Wang; Atabak Mahram; Wei Qin; Mrinal Bose; Jayanta Bhadra (ISVLSI, 2009)

Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning. - Chia-Ling Chang; Charles H.-P. Wen; Jayanta Bhadra (ITC, 2009)

Portable simulation/emulation stimulus on an industrial-strength SoC. - Francisco Torres; Rohit Srivastava; Javier Ruiz; Charles H.-P. Wen; Mrinal Bose; Jayanta Bhadra (ITC, 2009)

Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling. - Vyas Venkataraman; Di Wang; Wei Qin; Mrinal Bose; Jayanta Bhadra (MTV, 2009)

Modeling and verification of industrial flash memories. - Sandip Ray; Jayanta Bhadra; Thomas Portlock; Ronald Syzdek (ISQED, 2010)

A kernel-based approach for functional test program generation. - Po-Hsien Chang; Li-C. Wang; Jayanta Bhadra (ITC, 2010)

Innovative practices session 7C: Verification and testing challenges in high-level synthesis. - Sandip Ray; Jayanta Bhadra (VTS, 2010)

A Unified Formal Framework for Analyzing Functional and Speed-path Properties. - Oswaldo Olivo; Sandip Ray; Jayanta Bhadra; Vivekananda M. Vedula (MTV, 2011)

An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology. - Chia-Ling Chang; Chia-Ching Chang; Hui-Ling Chan; Charles H.-P. Wen; Jayanta Bhadra (ASP-DAC, 2012)

Novel test detection to improve simulation efficiency - A commercial experiment. - Wen Chen 016; Nik Sumikawa; Li-C. Wang; Jayanta Bhadra; Xiushan Feng; Magdy S. Abadir (ICCAD, 2012)

Introduction to special section on verification challenges in the concurrent world. - Sandip Ray; Jayanta Bhadra; Magdy S. Abadir; Li-C. Wang; Aarti Gupta (ACM Trans. Design Autom. Electr. Syst., 2012)

Simulation knowledge extraction and reuse in constrained random processor verification. - Wen Chen 016; Li-C. Wang; Jay Bhadra; Magdy S. Abadir (DAC, 2013)

Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step. - Chia-Ling Chang; Charles H.-P. Wen; Jayanta Bhadra (DATE, 2013)

Novel test analysis to improve structural coverage - A commercial experiment. - Wen Chen 016; Li-C. Wang; Jayanta Bhadra; Magdy S. Abadir (VLSI-DAT, 2013)

Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs. - Sandip Ray; Jay Bhadra; Magdy S. Abadir; Li-C. Wang (J. Electron. Test., 2013)

On application of data mining in functional debug. - Kuo-Kai Hsieh; Wen Chen 016; Li-C. Wang; Jayanta Bhadra (ICCAD, 2014)

Striking a balance between SoC security and debug requirements. - Wen Chen 016; Jayanta Bhadra (SoCC, 2016)

Security challenges in mobile and IoT systems. - Sandip Ray; Jayanta Bhadra (SoCC, 2016)

Feature extraction from design documents to enable rule learning for improving assertion coverage. - Kuo-Kai Hsieh; Sebastian Siatkowski; Li-C. Wang; Wen Chen 016; Jayanta Bhadra (ASP-DAC, 2017)

Learning to Produce Direct Tests for Security Verification Using Constrained Process Discovery. - Kuo-Kai Hsieh; Li-C. Wang; Wen Chen 016; Jayanta Bhadra (DAC, 2017)

Extensibility in Automotive Security: Current Practice and Challenges: Invited. - Sandip Ray; Wen Chen 016; Jayanta Bhadra; Mohammad Abdullah Al Faruque (DAC, 2017)

Guest Editors' Introduction: Emerging Challenges and Solutions in SoC Verification. - Magdy S. Abadir; Jayanta Bhadra; Wen Chen 016; Li-C. Wang (IEEE Des. Test, 2017)

Data-Driven Test Plan Augmentation for Platform Verification. - Wen Chen 016; Kuo-Kai Hsieh; Li-Chung Wang; Jayanta Bhadra (IEEE Des. Test, 2017)

Challenges and Trends in Modern SoC Design Verification. - Wen Chen 016; Sandip Ray; Jayanta Bhadra; Magdy S. Abadir; Li-C. Wang (IEEE Des. Test, 2017)

Practices and Challenges for Achieving Functional Safety of Modern Automotive SoCs. - Wen Chen 016; Jayanta Bhadra (IEEE Des. Test, 2019)