An algorithm for microcode compaction of VHDL behavioral descriptions. - Jayaram Bhasker (MICRO, 1987)

Compacting MIMOLA microcode. - Jayaram Bhasker; Tariq Samad (MICRO, 1987)

A linear time algorithm to check for the existence of a rectangular dual of a planar triangulated graph. - Jayaram Bhasker; Sartaj Sahni (Networks, 1987)

A Linear Algorithm to Find a Rectangular Dual of a Planar Triangulated Graph. - Jayaram Bhasker; Sartaj Sahni (Algorithmica, 1988)

Implementation of an optimizing compiler for VHDL. - Jayaram Bhasker (ACM SIGPLAN Notices, 1988)

Process-graph Analyser: A Front-end Tool for VHDL Behavioural Synthesis. - Jayaram Bhasker (Softw. Pract. Exp., 1988)

Via Assignment in Single-Row Routing. - Jayaram Bhasker; Sartaj Sahni (IEEE Trans. Computers, 1989)

An Optimizer for Hardware Synthesis. - Jayaram Bhasker; Huan-Chih Lee (IEEE Des. Test Comput., 1990)

Simulation-Based Verification for High-Level Synthesis. - Rolf Ernst; Jayaram Bhasker (IEEE Des. Test Comput., 1991)

Size, chromatic number, and connectivity. - Jayaram Bhasker; Tariq Samad; Douglas B. West (Graphs Comb., 1994)

Datapath synthesis using a problem-space genetic algorithm. - Muhammad K. Dhodhi; Frank H. Hielscher; Robert H. Storer; Jayaram Bhasker (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Die VHDL-Syntax. - Jayaram Bhasker (Markt und Technik, 1996)

Improving Design and Verification Productivity with VHDL-200x. - Stephen Bailey; Erich Marschner; Jayaram Bhasker; Jim Lewis; Peter J. Ashenden (DATE, 2004)