A design for testability scheme to reduce test application time in full scan. - Dhiraj K. Pradhan; Jayashree Saxena (VTS, 1992)

Desgin for Testability of Asynchronous Sequential Circuits. - Jayashree Saxena; Dhiraj K. Pradhan (ICCD, 1993)

A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits. - Jayashree Saxena; Dhiraj K. Pradhan (ITC, 1993)

A novel scheme to reduce test application time in circuits with full scan. - Dhiraj K. Pradhan; Jayashree Saxena (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Integrating Automated Diagnosis into the Testing and Failure Analysis Operations. - Kenneth M. Butler; Karl Johnson; Jeff Platt; Anjali Jones; Jayashree Saxena (ITC, 1996)

Bridging Fault Diagnosis in the Absence of Physical Information. - David B. Lavo; Tracy Larrabee; F. Joel Ferguson; Brian Chess; Jayashree Saxena; Kenneth M. Butler (ITC, 1997)

Automated Diagnosis in Testing and Failure Analysis. - Kenneth M. Butler; Karl Johnson; Jeff Platt; Anjali Kinra; Jayashree Saxena (IEEE Des. Test Comput., 1997)

IC diagnosis: preventing wars and war stories. - Jayashree Saxena (ITC, 1998)

On applying non-classical defect models to automated diagnosis. - Jayashree Saxena; Kenneth M. Butler; Hari Balachandran; David B. Lavo; Tracy Larrabee; F. Joel Ferguson; Brian Chess (ITC, 1998)

An empirical study on the effects of test type ordering on overall test efficiency. - Jayashree Saxena; Kenneth M. Butler (ITC, 2000)

Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. - Zoran Stanojevic; Hari Balachandran; D. M. H. Walker; Fred Lakbani; Jayashree Saxena; Kenneth M. Butler (ITC, 2000)

An analysis of power reduction techniques in scan testing. - Jayashree Saxena; Kenneth M. Butler; Lee Whetsel (ITC, 2001)

Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges . - Jayashree Saxena; Kenneth M. Butler; John Gatt; R. Raghuraman; Sudheendra Phani Kumar; Supatra Basu; David J. Campbell; John Berech (ITC, 2002)

A Case Study of IR-Drop in Structured At-Speed Testing. - Jayashree Saxena; Kenneth M. Butler; Vinay B. Jayaram; Subhendu Kundu; N. V. Arvind; Pravin Sreeprakash; Manfred Hachinger (ITC, 2003)

Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques. - Kenneth M. Butler; Jayashree Saxena; Tony Fryars; Graham Hetherington (ITC, 2004)

Modeling Test Escape Rate as a Function of Multiple Coverages. - Kenneth M. Butler; John M. Carulli Jr.; Jayashree Saxena (ITC, 2008)

Low Power Test for Nanometer System-on-Chips (SoCs). - Srivaths Ravi 001; Rubin A. Parekhji; Jayashree Saxena (J. Low Power Electron., 2008)

Multidimensional Test Escape Rate Modeling. - Kenneth M. Butler; John M. Carulli Jr.; Jayashree Saxena; Amit Nahar; W. Robert Daasch (IEEE Des. Test Comput., 2009)