Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation. - Lovleen Bhatia; Jayesh Gaur; Praveen Tiwari; Raj S. Mitra; Sunil H. Matange (DAC, 2007)

Bypass and insertion algorithms for exclusive last-level caches. - Jayesh Gaur; Mainak Chaudhuri; Sreenivas Subramoney (ISCA, 2011)

Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches. - Mainak Chaudhuri; Jayesh Gaur; Nithiyanandan Bashyam; Sreenivas Subramoney; Joseph Nuzman (PACT, 2012)

Efficient management of last-level caches in graphics processors for 3D scene rendering workloads. - Jayesh Gaur; Raghuram Srinivasan; Sreenivas Subramoney; Mainak Chaudhuri (MICRO, 2013)

Base-Victim Compression: An Opportunistic Cache Compression Architecture. - Jayesh Gaur; Alaa R. Alameldeen; Sreenivas Subramoney (ISCA, 2016)

Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources. - Jayesh Gaur; Mainak Chaudhuri; Pradeep Ramachandran; Sreenivas Subramoney (HPCA, 2017)

Micro-Sector Cache: Improving Space Utilization in Sectored DRAM Caches. - Mainak Chaudhuri; Mukesh Agrawal 001; Jayesh Gaur; Sreenivas Subramoney (ACM Trans. Archit. Code Optim., 2017)

Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache. - Kunal Korgaonkar; Ishwar Bhati; Huichu Liu; Jayesh Gaur; Sasikanth Manipatruni; Sreenivas Subramoney; Tanay Karnik; Steven Swanson; Ian Young 001; Hong Wang 003 (ISCA, 2018)

Criticality Aware Tiered Cache Hierarchy: A Fundamental Relook at Multi-Level Cache Hierarchies. - Anant Nori; Jayesh Gaur; Siddharth Rai; Sreenivas Subramoney; Hong Wang 003 (ISCA, 2018)

MARS: Memory Aware Reordered Source. - Ishwar Bhati; Udit Dhawan; Jayesh Gaur; Sreenivas Subramoney; Hong Wang 003 (CoRR, 2018)

Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth. - Mainak Chaudhuri; Jayesh Gaur; Sreenivas Subramoney (ICCD, 2019)

Post-silicon CPU adaptation made practical using machine learning. - Stephen J. Tarsa; Rangeen Basu Roy Chowdhury; Julien Sebot; Gautham N. Chinya; Jayesh Gaur; Karthik Sankaranarayanan; Chit-Kwan Lin; Robert Chappell; Ronak Singhal; Hong Wang (ISCA, 2019)

Focused Value Prediction. - Sumeet Bandishte; Jayesh Gaur; Zeev Sperber; Lihu Rappoport; Adi Yoaz; Sreenivas Subramoney (ISCA, 2020)

Auto-Predication of Critical Branches. - Adarsh Chauhan; Jayesh Gaur; Zeev Sperber; Franck Sala; Lihu Rappoport; Adi Yoaz; Sreenivas Subramoney (ISCA, 2020)

Stream Floating: Enabling Proactive and Decentralized Cache Optimizations. - Zhengrong Wang; Jian Weng 002; Jason Lowe-Power; Jayesh Gaur; Tony Nowatzki (HPCA, 2021)

Cryptographic Capability Computing. - Michael LeMay; Joydeep Rakshit; Sergej Deutsch; David M. Durham; Santosh Ghosh; Anant Nori; Jayesh Gaur; Andrew Weiler; Salmin Sultana; Karanvir Grewal; Sreenivas Subramoney (MICRO, 2021)

Register file prefetching. - Sudhanshu Shukla; Sumeet Bandishte; Jayesh Gaur; Sreenivas Subramoney (ISCA, 2022)

Speculative Code Compaction: Eliminating Dead Code via Speculative Microcode Transformations. - Logan Moody; Wei Qi; Abdolrasoul Sharifi; Layne Berry; Joey Rudek; Jayesh Gaur; Jeff Parkhurst; Sreenivas Subramoney; Kevin Skadron; Ashish Venkat (MICRO, 2022)

Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution. - Rahul Bera; Adithya Ranganathan; Joydeep Rakshit; Sujit Mahto; Anant V. Nori; Jayesh Gaur; Ataberk Olgun; Konstantinos Kanellopoulos; Mohammad Sadrosadati; Sreenivas Subramoney; Onur Mutlu (ISCA, 2024)