On Minimization of Peak Power for Scan Circuit during Test. - Jaynarayan T. Tudu; Erik Larsson; Virendra Singh; Vishwani D. Agrawal (ETS, 2009)

Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. - Jaynarayan T. Tudu; Erik Larsson; Virendra Singh; Hideo Fujiwara (ETS, 2010)

On selection of state variables for delay test of identical functional units. - Aditi Kajala; Gayaprasad Sinsinwar; Rahul Raj Choudhary; Jaynarayan T. Tudu; Virendra Singh (EWDTS, 2010)

Graph theoretic approach for scan cell reordering to minimize peak shift power. - Jaynarayan T. Tudu; Erik Larsson; Virendra Singh; Hideo Fujiwara (ACM Great Lakes Symposium on VLSI, 2010)

ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits. - Jaynarayan T. Tudu; Deepak Malani; Virendra Singh (VDAT, 2012)

Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP. - Jaynarayan T. Tudu; Deepak Malani; Virendra Singh (VDAT, 2013)

A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. - Satyadev Ahlawat; Jaynarayan T. Tudu; Anzhela Yu. Matrosova; Virendra Singh (ATS, 2015)

A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture. - Binod Kumar 001; Boda Nehru; Brajesh Pandey; Virendra Singh; Jaynarayan T. Tudu (EWDTS, 2016)

A high performance scan flip-flop design for serial and mixed mode scan test. - Satyadev Ahlawat; Jaynarayan T. Tudu; Anzhela Yu. Matrosova; Virendra Singh (IOLTS, 2016)

Skip-scan: A methodology for test time reduction. - Binod Kumar 001; Boda Nehru; Brajesh Pandey; Jaynarayan T. Tudu (VDAT, 2016)

On minimization of test power through modified scan flip-flop. - Satyadev Ahlawat; Jaynarayan T. Tudu (VDAT, 2016)

On determination of instantaneous peak and cycle peak switching using ILP. - Rohini Gulve; Nihar Hage; Jaynarayan T. Tudu (VDAT, 2016)

JSCAN: A joint-scan DFT architecture to minimize test time, pattern volume, and power. - Jaynarayan T. Tudu (VDAT, 2016)

Guided shifting of test pattern to minimize test time in serial scan. - Jaynarayan T. Tudu; Satyadev Ahlawat (VDAT, 2016)

On Securing Scan Design from Scan-Based Side-Channel Attacks. - Satyadev Ahlawat; Darshit Vaghani; Jaynarayan T. Tudu; Virendra Singh (ATS, 2017)

Revisiting random access scan for effective enhancement of post-silicon observability. - Binod Kumar 001; Ankit Jindal; Jaynarayan T. Tudu; Brajesh Pandey; Virendra Singh (IOLTS, 2017)

A Cost Effective Technique for Diagnosis of Scan Chain Faults. - Satyadev Ahlawat; Darshit Vaghani; Jaynarayan T. Tudu; Ashok Suhag (VDAT, 2017)

On Securing Scan Design Through Test Vector Encryption. - Darshit Vaghani; Satyadev Ahlawat; Jaynarayan T. Tudu; Masahiro Fujita; Virendra Singh (ISCAS, 2018)

Preventing Scan Attack through Test Response Encryption. - Satyadev Ahlawat; Jaynarayan T. Tudu; Manoj Singh Gaur; Masahiro Fujita; Virendra Singh (DFT, 2019)

Securing Scan through Plain-text Restriction. - Satyadev Ahlawat; Kailash Ahirwar; Jaynarayan T. Tudu; Masahiro Fujita; Virendra Singh (IOLTS, 2019)

LUT-based Circuit Approximation with Targeted Error Guarantees. - Vinod G. U; Vineesh V. S.; Jaynarayan T. Tudu; Masahiro Fujita; Virendra Singh (ATS, 2020)

A Framework for Configurable Joint-Scan Design-for-Test Architecture. - Jaynarayan T. Tudu; Satyadev Ahlawat; Sonali Shukla; Virendra Singh (J. Electron. Test., 2021)

On Protecting IJTAG from Data Sniffing and Alteration Attacks. - Anjum Riaz; Gaurav Kumar; Jaynarayan T. Tudu; Satyadev Ahlawat (ISVLSI, 2022)

Approximate Scan Flip-flop to Reduce Functional Path Delay and Power Consumption. - Lakshmi Bhanuprakash Reddy Konduru; Vijaya Lakshmi; Jaynarayan T. Tudu (CoRR, 2022)

Physical-Design Aware Scan Cell Reordering for Low Power Testing. - Rohit Badjatya; N. S. Vinay; Rahul Kumar; Jaynarayan T. Tudu; Masahiro Fujita; Virendra Singh (EWDTS, 2024)

AI-Driven Power Gating for Enhanced Energy Efficiency in Superscalar Processors. - Naman Kalra; Jaynarayan T. Tudu (HIPCW, 2024)

Near-Threshold-at-Gate based Test for Stuck-on Fault in Scan-chain Testing. - Haripriya R. S; Soumitro Vyapari; Jaynarayan T. Tudu (VLSID, 2024)

SiFFS: A Scalable in-Fault Functional Simulation Framework for Fault Criticality Analysis. - Haripriya R. S; Naveen Kollepara; Jaynarayan T. Tudu (ETS, 2025)

RL-Driven Fine-Grained Power Gating for Modern Processors Using Multi-Layer Perceptron Models. - Naman Kalra; Jaynarayan T. Tudu (ISQED, 2025)