A 55nm 1GHz one-cycle-locking de-skewing circuit. - Jinn-Shyan Wang; Chun-Yuan Cheng; Je-Ching Liu; Yu-Chia Liu; Yi-Ming Wang (ISCAS, 2010)

A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop. - Jinn-Shyan Wang; Chun-Yuan Cheng; Je-Ching Liu; Yu-Chia Liu; Yi-Ming Wang (IEEE J. Solid State Circuits, 2010)