A 2.2mW 12-bit 200MS/s 28nm CMOS Pipelined SAR ADC with Dynamic Register-Based High-Speed SAR Logic. - Jun-Sang Park; Je-Min Jeon; Jun-Ho Boo; Jae-Hyuk Lee; Kang-Il Cho; Ho-Jin Kim; Gil-Cho Ahn; Seung-Hoon Lee 006 (A-SSCC, 2020)