A data flow architecture with a paged memory system. - L. J. Caluwaerts; J. Debacker; J. A. Peperstraete (ISCA, 1982)

Implementing Streams on a Data Flow Computer System With Paged Memory - L. J. Caluwaerts; J. Debacker; J. A. Peperstraete (ISCA, 1983)

An Integrated Software-Hardware Multiprocesor Project. - Rudy Lauwereins; J. A. Peperstraete (ICPP, 1987)

Parallel processing enables the real-time emulation of DSP ASICs. - Rudy Lauwereins; Marc Engels; J. A. Peperstraete (RSP, 1990)

A Powerful Hig-Level Debugger for Parallel Programs. - Chris Caerts; Rudy Lauwereins; J. A. Peperstraete (ACPC, 1991)

Rapid Prototyping for DSP Systems with Multiprocessors. - Marc Engels; Rudy Lauwereins; J. A. Peperstraete (IEEE Des. Test Comput., 1991)

GRAPE-II: a tool for the rapid prototyping of multi-rate asynchronous DSP applications on heterogeneous multiprocessors. - Rudy Lauwereins; Marc Engels; J. A. Peperstraete (RSP, 1992)

Efficient decomposition of comparison and its applications. - Valeriu Beiu; J. A. Peperstraete; Joos Vandewalle; Rudy Lauwereins (ESANN, 1993)

Development of a load balancing tool for the GRAPE rapid prototyping environment. - Greet Bilsen; Marc Engels; Rudy Lauwereins; Jean A. Peperstraete (RSP, 1993)

PDG: a process-level debugger for concurrent programs in the GRAPE rapid prototyping environment. - Chris Caerts; Rudy Lauwereins; Jean A. Peperstraete (RSP, 1993)

Design of a processing board for a programmable multi-VSP system. - Marc Engels; Rudy Lauwereins; J. A. Peperstraete; Arthur H. M. van Roermund (J. VLSI Signal Process., 1993)

Control of a Dead-time Process by a Fuzzy Algorithm. - Manga J. P. Bekambo; J. A. Peperstraete (Applied Informatics, 1994)

VLSI complexity reduction by piece-wise approximation of the sigmoid function. - Valeriu Beiu; J. A. Peperstraete; Joos Vandewalle; Rudy Lauwereins (ESANN, 1994)

PDG: A Portable Process-Level Debugger for CSP-Style Parallel Programs. - Chris Caerts; Rudy Lauwereins; J. A. Peperstraete (HICSS (2), 1994)

Buffer memory requirements in DSP applications. - Marleen Adé; Rudy Lauwereins; J. A. Peperstraete (RSP, 1994)

Geometric parallelism and cyclo-static data flow in GRAPE-II. - Rudy Lauwereins; Piet Wauters; Marleen Adé; J. A. Peperstraete (RSP, 1994)

Fault-Tolerant Compact Routing Based on Reduced Structural Information in Wormhole-Switching Based Networks. - Johan Vounckx; Geert Deconinck; Rudy Lauwereins; J. A. Peperstraete (SIROCCO, 1994)

Closse Approximations of Sigmoid Functions by Sum of Step for VLSI Implementation of Neural Networks. - Valeriu Beiu; J. A. Peperstraete; Joos Vandewalle; Rudy Lauwereins (Sci. Ann. Cuza Univ., 1994)

Kernel services approach to fault-masking in real-time applications. - Manga J. P. Bekambo; Johan Vounckx; Geert Deconinck; R. Cuyvers; Rudy Lauwereins; J. A. Peperstraete (RTS, 1995)

Compile-time scheduling with resource-constraints. - Greet Bilsen; Rudy Lauwereins; J. A. Peperstraete (HICSS (2), 1995)

Cyclo-static data flow. - Greet Bilsen; Marc Engels; Rudy Lauwereins; Jean A. Peperstraete (ICASSP, 1995)

A User-triggered Checkpointing Library for Computationintensive Applications. - Geert Deconinck; Johan Vounckx; Rudy Lauwereins; J. A. Peperstraete (Parallel and Distributed Computing and Systems, 1995)

A User-Adaptable Fault Tolerant Motor Controller using an Argument Flow Multiprocessor System. - J. A. Peperstraete; R. Cuyvers; Rudy Lauwereins (Parallel and Distributed Computing and Systems, 1995)

A Loader for Injured Massively Parallel Regular Networks. - Johan Vounckx; Geert Deconinck; Rudy Lauwereins; J. A. Peperstraete (Parallel and Distributed Computing and Systems, 1995)

Hardware-software codesign with GRAPE. - Marleen Adé; Rudy Lauwereins; J. A. Peperstraete (RSP, 1995)

Grape-II: A System-Level Prototyping Environment for DSP Applications. - Rudy Lauwereins; Marc Engels; Marleen Adé; J. A. Peperstraete (Computer, 1995)

PDG: A process-level debugger for concurrent programs in the GRAPE parallel programming environment. - Chris Caerts; Rudy Lauwereins; Jean A. Peperstraete (Future Gener. Comput. Syst., 1995)

Global Approach for Compiled Bit-True Simulation of DSP Systems. - Luc De Coster; Marc Engels; Rudy Lauwereins; J. A. Peperstraete (Euro-Par, Vol. II, 1996)

Cyclo-Dynamic Dataflow. - Piet Wauters; Marc Engels; Rudy Lauwereins; J. A. Peperstraete (PDP, 1996)

Implementing DSP applications on heterogeneous targets using minimal size data buffers. - Marleen Adé; Rudy Lauwereins; J. A. Peperstraete (RSP, 1996)

Cycle-static dataflow. - Greet Bilsen; Marc Engels; Rudy Lauwereins; J. A. Peperstraete (IEEE Trans. Signal Process., 1996)

Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets. - Marleen Adé; Rudy Lauwereins; J. A. Peperstraete (DAC, 1997)

Data routing in dataflow graphs. - Luc De Coster; Rudy Lauwereins; J. A. Peperstraete (IEEE International Workshop on Rapid System Prototyping, 1997)

Code Generation for Compiled Bit-True Simulation of DSP Applications. - Luc De Coster; Marleen Adé; Rudy Lauwereins; J. A. Peperstraete (ISSS, 1998)

Rapid prototyping of an adaptive noise canceler using GRAPE. - Luc De Coster; Rudy Lauwereins; J. A. Peperstraete (Signal Process., 1998)