Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. - Jean-Baptiste Rigaud; Jerome Quartana; Laurent Fesquet; Marc Renaudin (VLSI-SOC, 2001)

High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. - Jean-Baptiste Rigaud; Laurent Fesquet; Marc Renaudin; Jerome Quartana (DATE, 2002)

Implementing Asynchronous Circuits on LUT Based FPGAs. - Quoc Thai Ho; Jean-Baptiste Rigaud; Laurent Fesquet; Marc Renaudin; Robin Rolland (FPL, 2002)

Spécification de bibliothèques pour la synthèse de circuits asynchrones. (Libraries specification for the synthesis of asynchronous circuits). - Jean-Baptiste Rigaud (2002)

An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. - Dominique Borrione; Menouer Boubekeur; Emil Dumitrescu; Marc Renaudin; Jean-Baptiste Rigaud; Antoine Siriani (HICSS, 2003)

Statistic Implementation of QDI Asynchronous Primitives. - Philippe Maurine; Jean-Baptiste Rigaud; G. Fraidy Bouesse; Gilles Sicard; Marc Renaudin (PATMOS, 2003)

Hardware Engines for Bus Encryption: A Survey of Existing Techniques. - Reouven Elbaz; Lionel Torres; Gilles Sassatelli; Pierre Guillemin; C. Anguille; Michel Bardouillet; Christian Buatois; Jean-Baptiste Rigaud (DATE, 2005)

Integrated Evaluation Platform for Secured Devices. - Pascal Manet; Jean-Baptiste Rigaud; Julien Francq; Marc Jeambrun; Assia Tria; Bruno Robisson; Jerome Quartana; Selma Laabidi (ReCoSoC, 2006)

Experimental evaluation of protections against laser-induced faults and consequences on fault modeling. - Régis Leveugle; Abdelaziz Ammari; V. Maingot; E. Teyssou; Pascal Moitrel; Christophe Mourtel; Nathalie Feyt; Jean-Baptiste Rigaud; Assia Tria (DATE, 2007)

Strengthening hardware AES implementations against fault attacks. - Marc Joye; Pascal Manet; Jean-Baptiste Rigaud (IET Inf. Secur., 2007)

Error Detection for Borrow-Save Adders Dedicated to ECC Unit. - Julien Francq; Jean-Baptiste Rigaud; Pascal Manet; Assia Tria; Arnaud Tisserand (FDTC, 2008)

Experimental Fault Injection based on the Prototyping of an AES Cryptosystem. - Jean-Baptiste Rigaud; Jean-Max Dutertre; Michel Agoyan; Bruno Robisson; Assia Tria (ReCoSoC, 2010)

A side-channel and fault-attack resistant AES circuit working on duplicated complemented values. - Marion Doulcier-Verdier; Jean-Max Dutertre; Jacques J. A. Fournier; Jean-Baptiste Rigaud; Bruno Robisson; Assia Tria (ISSCC, 2011)

Design and characterisation of an AES chip embedding countermeasures. - Jacques J. A. Fournier; Jean-Baptiste Rigaud; Sylvain Bouquet; Bruno Robisson; Assia Tria; Jean-Max Dutertre; Michel Agoyan (Int. J. Intell. Eng. Informatics, 2011)

Power analysis methodology for secure circuits. - Kamil Gomina; Jean-Baptiste Rigaud; Philippe Gendrier; Philippe Candelier; Assia Tria (DDECS, 2013)

Voltage Glitch Attacks on Mixed-Signal Systems. - Noemie Beringuier-Boher; Kamil Gomina; David Hély; Jean-Baptiste Rigaud; Vincent Beroulle; Assia Tria; Joel Damiens; Philippe Gendrier; Philippe Candelier (DSD, 2014)

Detecting positive voltage attacks on CMOS circuits. - Kamil Gomina; Philippe Gendrier; Philippe Candelier; Jean-Baptiste Rigaud; Assia Tria (CS2@HiPEAC, 2014)

Power supply glitch attacks: Design and evaluation of detection circuits. - Kamil Gomina; Jean-Baptiste Rigaud; Philippe Gendrier; Philippe Candelier; Assia Tria (HOST, 2014)

Analysis Of Variance and CPA in SCA. - Sébastien Tiran; Guillaume Reymond; Jean-Baptiste Rigaud; Driss Aboulkassimi; Benedikt Gierlichs; Mathieu Carbone; Gilles R. Ducharme; Philippe Maurine (IACR Cryptol. ePrint Arch., 2014)

Hardware trojan detection by delay and electromagnetic measurements. - Xuan Thuy Ngo; Ingrid Exurville; Shivam Bhasin; Jean-Luc Danger; Sylvain Guilley; Zakaria Najm; Jean-Baptiste Rigaud; Bruno Robisson (DATE, 2015)

Evidence of an information leakage between logically independent blocks. - Loïc Zussa; Ingrid Exurville; Jean-Max Dutertre; Jean-Baptiste Rigaud; Bruno Robisson; Assia Tria; Jessy Clédière (CS2@HiPEAC, 2015)

Resilient hardware Trojans detection based on path delay measurements. - Ingrid Exurville; Loïc Zussa; Jean-Baptiste Rigaud; Bruno Robisson (HOST, 2015)

Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses. - Marc Lacruche; Nicolas Borrel; Clement Champeix; Cyril Roscian; Alexandre Sarafianos; Jean-Baptiste Rigaud; Jean-Max Dutertre; Edith Kussener (IOLTS, 2015)

High-Performance Elliptic Curve Cryptography by Using the CIOS Method for Modular Multiplication. - Amine Mrabet; Nadia El Mrabet; Ronan Lashermes; Jean-Baptiste Rigaud; Belgacem Bouallegue; Sihem Mesnager; Mohsen Machhout (CRiSIS, 2016)

A fully-digital EM pulse detector. - David El-Baze; Jean-Baptiste Rigaud; Philippe Maurine (DATE, 2016)

On the use of Forward Body Biasing to decrease the repeatability of laser-induced faults. - Marc Lacruche; Noemie Beringuier-Boher; Jean-Max Dutertre; Jean-Baptiste Rigaud; Edith Kussener (DATE, 2016)

An Embedded Digital Sensor against EM and BB Fault Injection. - David El-Baze; Jean-Baptiste Rigaud; Philippe Maurine (FDTC, 2016)

Body Biasing Injection Attacks in Practice. - Noemie Beringuier-Boher; Marc Lacruche; David El-Baze; Jean-Max Dutertre; Jean-Baptiste Rigaud; Philippe Maurine (CS2@HiPEAC, 2016)

A Systolic Hardware Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems. - Amine Mrabet; Nadia El Mrabet; Ronan Lashermes; Jean-Baptiste Rigaud; Belgacem Bouallegue; Sihem Mesnager; Mohsen Machhout (IACR Cryptol. ePrint Arch., 2016)

A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs. - Amine Mrabet; Nadia El Mrabet; Ronan Lashermes; Jean-Baptiste Rigaud; Belgacem Bouallegue; Sihem Mesnager; Mohsen Machhout (J. Hardw. Syst. Secur., 2017)

Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller. - Brice Colombier; Alexandre Menu; Jean-Max Dutertre; Pierre-Alain Moëllic; Jean-Baptiste Rigaud; Jean-Luc Danger (IACR Cryptol. ePrint Arch., 2018)

Precise Spatio-Temporal Electromagnetic Fault Injections on Data Transfers. - Alexandre Menu; Shivam Bhasin; Jean-Max Dutertre; Jean-Baptiste Rigaud; Jean-Luc Danger (FDTC, 2019)

Experimental Analysis of the Laser-Induced Instruction Skip Fault Model. - Jean-Max Dutertre; Timothée Riom; Olivier Potin; Jean-Baptiste Rigaud (NordSec, 2019)

Experimental Analysis of the Electromagnetic Instruction Skip Fault Model. - Alexandre Menu; Jean-Max Dutertre; Olivier Potin; Jean-Baptiste Rigaud; Jean-Luc Danger (DTIS, 2020)

Single-bit Laser Fault Model in NOR Flash Memories: Analysis and Exploitation. - Alexandre Menu; Jean-Max Dutertre; Jean-Baptiste Rigaud; Brice Colombier; Pierre-Alain Moëllic; Jean-Luc Danger (FDTC, 2020)

Evidence of a Dynamic Fault Model in the DICE Radiation-Hardened Cell. - William Souza da Cruz; Jean-Max Dutertre; Jean-Baptiste Rigaud; Guillaume Hubert (SBCCI, 2020)

Multiplication over Extension Fields for Pairing-based Cryptography: an Hardware Point of View. - Arthur Lavice; Nadia El Mrabet; Alexandre Berzati; Jean-Baptiste Rigaud (IACR Cryptol. ePrint Arch., 2020)

Further Analysis of Laser-induced IR-drop. - William Souza da Cruz; Raphael Andreoni Camponogara Viera; Jean-Max Dutertre; Jean-Baptiste Rigaud; Guillaume Hubert (ATS, 2021)

Hardware Implementations of Pairings at Updated Security Levels. - Arthur Lavice; Nadia El Mrabet; Alexandre Berzati; Jean-Baptiste Rigaud; Julien Proy (CARDIS, 2021)

Hardware Implementation of Multiplication over Quartic Extension Fields. - Arthur Lavice; Nadia El Mrabet; Alexandre Berzati; Jean-Baptiste Rigaud (ICMC, 2021)

A Review of Confidentiality Threats Against Embedded Neural Network Models. - Raphaël Joud; Pierre-Alain Moëllic; Rémi Bernhard; Jean-Baptiste Rigaud (WF-IoT, 2021)

A Practical Introduction to Side-Channel Extraction of Deep Neural Network Parameters. - Raphaël Joud; Pierre-Alain Moëllic; Simon Pontié; Jean-Baptiste Rigaud (CARDIS, 2022)

A CFI Verification System based on the RISC-V Instruction Trace Encoder. - Anthony Zgheib; Olivier Potin; Jean-Baptiste Rigaud; Jean-Max Dutertre (DSD, 2022)

CMOS/STT-MRAM Based Ascon LWC: a Power Efficient Hardware Implementation. - Nathan Roussel; Olivier Potin; Gregory di Pendina; Jean-Max Dutertre; Jean-Baptiste Rigaud (ICECS 2022, 2022)

An Experimentally Tuned Compact Electrical Model for Laser Fault Injection Simulation. - William Souza da Cruz; Raphael Viera 001; Jean-Baptiste Rigaud; Guillaume Hubert; Jean-Max Dutertre (IOLTS, 2022)

Like an Open Book? Read Neural Network Architecture with Simple Power Analysis on 32-Bit Microcontrollers. - Raphaël Joud; Pierre-Alain Moëllic; Simon Pontié; Jean-Baptiste Rigaud (CARDIS, 2023)

A CCFI Verification Scheme Based on the RISC-V Trace Encoder. - Anthony Zgheib; Olivier Potin; Jean-Baptiste Rigaud; Jean-Max Dutertre (COSADE, 2023)

Highlighting Two EM Fault Models While Analyzing a Digital Sensor Limitations. - Roukoz Nabhan; Jean-Max Dutertre; Jean-Baptiste Rigaud; Jean-Luc Danger; Laurent Sauvage (DATE, 2023)

Security Evaluation of a Hybrid CMOS/MRAM Ascon Hardware Implementation. - Nathan Roussel; Olivier Potin; Jean-Max Dutertre; Jean-Baptiste Rigaud (DATE, 2023)

A Tale of Two Models: Discussing the Timing and Sampling EM Fault Injection Models. - Roukoz Nabhan; Jean-Max Dutertre; Jean-Baptiste Rigaud; Jean-Luc Danger; Laurent Sauvage (FDTC, 2023)

Lightweight Countermeasures Against Original Linear Code Extraction Attacks on a RISC-V Core. - Théophile Gousselot; Olivier Thomas; Jean-Max Dutertre; Olivier Potin; Jean-Baptiste Rigaud (HOST, 2023)

CIFER: Code Integrity and control Flow verification for programs Executed on a RISC-V core. - Anthony Zgheib; Olivier Potin; Jean-Baptiste Rigaud; Jean-Max Dutertre (HOST, 2023)

Experimental EMFI detection on a RISC-V core using the Trace Verifier solution. - Anthony Zgheib; Olivier Potin; Jean-Baptiste Rigaud; Jean-Max Dutertre (Microprocess. Microsystems, 2023)

Analysis and Mitigation of Hybrid CMOS/MRAM DFF Vulnerabilities to Laser Fault Injection. - Raphaël Comps; Jean-Baptiste Rigaud; Jean-Max Dutertre (AsianHOST, 2024)

Using a Performance Model to Implement a Superscalar CVA6. - Côme Allart; Jean-Roch Coulon; André Sintzoff; Olivier Potin; Jean-Baptiste Rigaud (CF (Companion), 2024)

EM Fault Injection-Induced Clock Glitches: From Mechanism Analysis to Novel Sensor Design. - Roukoz Nabhan; Jean-Max Dutertre; Jean-Baptiste Rigaud; Jean-Luc Danger; Laurent Sauvage (IOLTS, 2024)

Code Encryption for Confidentiality and Execution Integrity Down to Control Signals. - Théophile Gousselot; Jean-Max Dutertre; Olivier Potin; Jean-Baptiste Rigaud (HOST, 2025)

Betrayed by Light: How Photon Emission Microscopy Empowers Register Bit-Level Laser Attacks on Microcontrollers. - Hugo Perrin; Jean-Max Dutertre; Jean-Baptiste Rigaud (HOST, 2025)

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture. - Riccardo Tedeschi; Gianmarco Ottavi; Côme Allart; Nils Wistoff; Zexin Fu; Filippo Grillotti; Fabio De Ambroggi; Elio Guidetti; Jean-Baptiste Rigaud; Olivier Potin; Jean-Roch Coulon; César Fuguet; et al. (CoRR, 2025)