A real-time VLSI-based architecture for multi-motion estimation. - Jean-Didier Legat; J. P. Cornil; Damien Macq; Michel Verleysen (ICPR (4), 1992)

Optimal decision surfaces in LVQ1 classiffication of patterns. - Michel Verleysen; Philippe Thissen; Jean-Didier Legat (ESANN, 1993)

Linear Vector Classification: An Improvement on LVQ Algorithms to Create Classes of Patterns. - Michel Verleysen; Philippe Thissen; Jean-Didier Legat (IWANN, 1993)

Systolic implementation of a bidimensional lattice filter bank for multiresolution image coding. - Pierre Desneux; Jean-Didier Legat; Benoît Macq; Jean-Yves Mertès (VCIP, 1993)

Analog implementation of a Kohonen map with on-chip learning. - Damien Macq; Michel Verleysen; Paul G. A. Jespers; Jean-Didier Legat (IEEE Trans. Neural Networks, 1993)

Suboptimal Bayesian classification by vector quantization with small clusters. - Jean-Luc Voz; Michel Verleysen; Philippe Thissen; Jean-Didier Legat (ESANN, 1995)

A statistical neural network for high-dimensional vector classification. - Michel Verleysen; Jean-Luc Voz; Philippe Thissen; Jean-Didier Legat (ICNN, 1995)

An Associative Processor Dedicated to Classification by Neural Methods. - Philippe Thissen; Michel Verleysen; Jean-Didier Legat (IWANN, 1995)

A VLSI System for Neural Bayesian and LVQ Classification. - Philippe Thissen; Michel Verleysen; Jean-Didier Legat; Jordi Madrenas; Jordi Domínguez (IWANN, 1995)

A Practical View of Suboptimal Bayesian Classification with Radial Gaussian Kernels. - Jean-Luc Voz; Michel Verleysen; Philippe Thissen; Jean-Didier Legat (IWANN, 1995)

Resolution reduction by growth of zones for visual prosthesis. - Tanguy Gilmont; Xavier Verians; Jean-Didier Legat; Claude Veraart (ICIP (1), 1996)

Efficient Parallelisation of an MPEG-2 Codec on a TMS320C80 Video Processor. - Olivier Cantineau; Jean-Didier Legat (ICIP (3), 1998)

A Data-Flow Oriented Co-Design for Reconfigurable Systems. - Jean-Pierre David; Jean-Didier Legat (International Workshop on Rapid System Prototyping, 1998)

Selective prediction error transmission using motion information. - Emmanuel Hanssens; Bertrand Chupeau; Jean-Didier Legat; Benoît Macq (Signal Process. Image Commun., 1998)

Image compression by self-organized Kohonen map. - C. Amerijckx; Michel Verleysen; Philippe Thissen; Jean-Didier Legat (IEEE Trans. Neural Networks, 1998)

Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit. - Olivier Cantineau; Laurent Petit; Jean-Didier Legat (J. VLSI Signal Process., 1998)

A New Parallelism Management Scheme for Multiprocessor Systems. - Xavier Verians; Jean-Didier Legat; Jean-Jacques Quisquater; Benoît Macq (ACPC, 1999)

Enhancing Security in the Memory Management Unit. - Tanguy Gilmont; Jean-Didier Legat; Jean-Jacques Quisquater (EUROMICRO, 1999)

A Graph-Oriented Task Manager for Small Multiprocessor Systems. - Xavier Verians; Jean-Didier Legat; Jean-Jacques Quisquater; Benoît Macq (Euro-Par, 1999)

Fine grain parallelization of multibody system equations of motion. - Tony Postiau; Paul Fisette; Jean-Didier Legat (PARCO, 1999)

Architecture of security management unit for safe hosting of multiple agents. - Tanguy Gilmont; Jean-Didier Legat; Jean-Jacques Quisquater (Security and Watermarking of Multimedia Contents, 1999)

A dedicated DSP architecture for discrete wavelet transform. - Pierre Desneux; Jean-Didier Legat (Integr. Comput. Aided Eng., 2000)

Implementation of very large dataflow graphs on a reconfigurable architecture for robotic applications. - Jean-Pierre David; Tony Postiau; Paul Fisette; Jean-Didier Legat (IPDPS, 2001)

A Time-Memory Tradeoff Using Distinguished Points: New Analysis & FPGA Results. - François-Xavier Standaert; Gaël Rouvroy; Jean-Jacques Quisquater; Jean-Didier Legat (CHES, 2002)

RASH: RAdon soft hash algorithm. - Frédéric Lefèbvre; Benoît Macq; Jean-Didier Legat (EUSIPCO, 2002)

An FPGA Implementation of the Linear Cryptanalysis. - François Koeune; Gaël Rouvroy; François-Xavier Standaert; Jean-Jacques Quisquater; Jean-Pierre David; Jean-Didier Legat (FPL, 2002)

A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation. - Jean-Jacques Quisquater; François-Xavier Standaert; Gaël Rouvroy; Jean-Pierre David; Jean-Didier Legat (FPL, 2002)

Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs. - François-Xavier Standaert; Gaël Rouvroy; Jean-Jacques Quisquater; Jean-Didier Legat (CHES, 2003)

Design strategies and modified descriptions to optimize cipher FPGA implementations: fast and compact results for DES and triple-DES. - Gaël Rouvroy; François-Xavier Standaert; Jean-Jacques Quisquater; Jean-Didier Legat (FPGA, 2003)

A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL. - François-Xavier Standaert; Gaël Rouvroy; Jean-Jacques Quisquater; Jean-Didier Legat (FPGA, 2003)

Efficient FPGA Implementation of Block Cipher MISTY1. - Gaël Rouvroy; François-Xavier Standaert; Jean-Jacques Quisquater; Jean-Didier Legat (IPDPS, 2003)

A survey on industrial vision systems, applications, tools. - Elias N. Malamas; Euripides G. M. Petrakis; Michalis E. Zervakis; Laurent Petit; Jean-Didier Legat (Image Vis. Comput., 2003)

Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Cryptanalysis. - Gaël Rouvroy; François-Xavier Standaert; Jean-Jacques Quisquater; Jean-Didier Legat (IEEE Trans. Computers, 2003)

Combined line-based architecture for the 5-3 and 9-7 wavelet transform of JPEG2000. - Grégory Dillen; Benoît Georis; Olivier Cantineau; Jean-Didier Legat (IEEE Trans. Circuits Syst. Video Technol., 2003)

Reconfigurable hardware solutions for the digital rights management of digital cinema. - Gaël Rouvroy; François-Xavier Standaert; Frédéric Lefèbvre; Jean-Jacques Quisquater; Benoît Macq; Jean-Didier Legat (Digital Rights Management Workshop, 2004)

An efficient FPGA implementation of a flexible JPEG2000 decoder for Digital Cinema. - Antonin Descampe; François-Olivier Devaux; Gaël Rouvroy; Benoît Macq; Jean-Didier Legat (EUSIPCO, 2004)

Hardware implementation of a fingerprinting algorithm suited for digital cinema. - Gaël Rouvroy; Frédéric Lefèbvre; François-Xavier Standaert; Benoît Macq; Jean-Jacques Quisquater; Jean-Didier Legat (EUSIPCO, 2004)

ICEBERG : An Involutional Cipher Efficient for Block Encryption in Reconfigurable Hardware. - François-Xavier Standaert; Gilles Piret; Gaël Rouvroy; Jean-Jacques Quisquater; Jean-Didier Legat (FSE, 2004)

Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications. - Gaël Rouvroy; François-Xavier Standaert; Jean-Jacques Quisquater; Jean-Didier Legat (ITCC (2), 2004)

Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell. - Ilham Hassoune; Amaury Nève; Jean-Didier Legat; Denis Flandre (PATMOS, 2004)

Practical Evaluation of a Radial Soft Hash Algorithm. - François-Xavier Standaert; Frédéric Lefèbvre; Gaël Rouvroy; Benoît Macq; Jean-Jacques Quisquater; Jean-Didier Legat (ITCC (2), 2005)

A Design Methodology for Secured ICs Using Dynamic Current Mode Logic. - François Macé; François-Xavier Standaert; Jean-Jacques Quisquater; Jean-Didier Legat (PATMOS, 2005)

Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. - Philippe Manet; David Bol; Renaud Ambroise; Jean-Didier Legat (PATMOS, 2005)

Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards. - Guerric Meurice de Dormale; Renaud Ambroise; David Bol; Jean-Jacques Quisquater; Jean-Didier Legat (ASAP, 2006)

Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses. - Hans Vandierendonck; Philippe Manet; Jean-Didier Legat (DATE, 2006)

Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison. - David Bol; Jean-Didier Legat; José M. Quintana; Maria José Avedillo (ICECS, 2006)

Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. - Philippe Manet; Renaud Ambroise; David Bol; Marc Baltus; Jean-Didier Legat (J. Low Power Electron., 2006)

Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks. - Ilham Hassoune; François Macé; Denis Flandre; Jean-Didier Legat (Microelectron. J., 2006)

A Flexible Hardware JPEG 2000 Decoder for Digital Cinema. - Antonin Descampe; François-Olivier Devaux; Gaël Rouvroy; Jean-Didier Legat; Jean-Jacques Quisquater; Benoît Macq (IEEE Trans. Circuits Syst. Video Technol., 2006)

By-passing the out-of-order execution pipeline to increase energy-efficiency. - Hans Vandierendonck; Philippe Manet; Thibault Delavallee; Igor Loiselle; Jean-Didier Legat (Conf. Computing Frontiers, 2007)

Interactive presentation: RECOPS: reconfiguring programmable devices for military hardware electronics. - Philippe Manet; Daniel Maufroid; Leonardo Tosi; Marco Di Ciano; Olivier Mulertt; Yves Gabriel; Jean-Didier Legat; Denis Aulagnier; Christian Gamrat; Raffaele Liberati; Vincenzo La Barba (DATE, 2007)

Enabling certification for dynamic partial reconfiguration using a minimal flow. - Bertrand Rousseau; Philippe Manet; D. Galerin; D. Merkenbreack; Jean-Didier Legat; F. Dedeken; Yves Gabriel (DATE, 2007)

NoC Implementation in FPGA Using Torus Topology. - Angelo Kuti Lusala; Philippe Manet; Bertrand Rousseau; Jean-Didier Legat (FPL, 2007)

Building Ultra-Low-Power Low-Frequency Digital Circuits with High-Speed Devices. - David Bol; Renaud Ambroise; Denis Flandre; Jean-Didier Legat (ICECS, 2007)

Dynamic differential self-timed logic families for robust and low-power security ICs. - Ilham Hassoune; François Macé; Denis Flandre; Jean-Didier Legat (Integr., 2007)

Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder. - David Bol; Ilham Hassoune; David Levacq; Denis Flandre; Jean-Didier Legat (J. Multiple Valued Log. Soft Comput., 2007)

Analysis and minimization of practical energy in 45nm subthreshold logic circuits. - David Bol; Renaud Ambroise; Denis Flandre; Jean-Didier Legat (ICCD, 2008)

Impact of Technology Scaling on Digital Subthreshold Circuits. - David Bol; Renaud Ambroise; Denis Flandre; Jean-Didier Legat (ISVLSI, 2008)

An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications. - Philippe Manet; Daniel Maufroid; Leonardo Tosi; Grégory Gailliard; Olivier Mulertt; Marco Di Ciano; Jean-Didier Legat; Denis Aulagnier; Christian Gamrat; Raffaele Liberati; Vincenzo La Barba; Pol Cuvelier; et al. (EURASIP J. Embed. Syst., 2008)

Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits. - David Bol; Denis Flandre; Jean-Didier Legat (ISLPED, 2009)

Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic. - David Bol; Dina Kamel; Denis Flandre; Jean-Didier Legat (ISLPED, 2009)

Flexible embedded system for sensor integration and custom data processing in an automotive application. - Lotfi Guedria; Damien Hubaux; Mathieu Ocaña; Jean-Didier Legat (IWCMC, 2009)

Interests and Limitations of Technology Scaling for Subthreshold Logic. - David Bol; Renaud Ambroise; Denis Flandre; Jean-Didier Legat (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms. - Bertrand Rousseau; Philippe Manet; Igor Loiselle; Jean-Didier Legat; Hans Vandierendonck (DASIP, 2010)

The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic. - David Bol; Cédric Hocquet; Denis Flandre; Jean-Didier Legat (ESSCIRC, 2010)

Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits. - David Bol; Cédric Hocquet; Denis Flandre; Jean-Didier Legat (ISCAS, 2010)

Combining circuit and packet switching with bus architecture in a NoC for real-time applications. - Angelo Kuti Lusala; Jean-Didier Legat (ISCAS, 2010)

A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching for On-chip Networks. - Angelo Kuti Lusala; Jean-Didier Legat (ReConFig, 2010)

ULPFA: A New Efficient Design of a Power-Aware Full Adder. - Ilham Hassoune; Denis Flandre; Ian O'Connor; Jean-Didier Legat (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic - Mitigation at Technology and Circuit Levels. - David Bol; Denis Flandre; Jean-Didier Legat (ACM Trans. Design Autom. Electr. Syst., 2010)

Combining sdm-based circuit switching with packet switching in a NoC for real-time applications. - Angelo Kuti Lusala; Jean-Didier Legat (ISCAS, 2011)

A new mechanism to reduce congestion on TDM networks-on-chips. - Daniel Vergeylen; Angelo Kuti Lusala; Jean-Didier Legat (ReCoSoC, 2011)

Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags. - Cédric Hocquet; Dina Kamel; Francesco Regazzoni 001; Jean-Didier Legat; Denis Flandre; David Bol; François-Xavier Standaert (J. Cryptogr. Eng., 2011)

A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes. - David Bol; Julien De Vos; Cédric Hocquet; François Botman; François Durvaux; Sarah Boyd; Denis Flandre; Jean-Didier Legat (ISSCC, 2012)

A hybrid NoC combining SDM-TDM based circuit-switching with packet-switching for real-time applications. - Angelo Kuti Lusala; Jean-Didier Legat (NEWCAS, 2012)

MPSoCDK: A framework for prototyping and validating MPSoC projects on FPGAs. - Renaud Van Langendonck; Angelo Kuti Lusala; Jean-Didier Legat (ReCoSoC, 2012)

Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks. - Angelo Kuti Lusala; Jean-Didier Legat (Int. J. Reconfigurable Comput., 2012)

A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks. - Angelo Kuti Lusala; Jean-Didier Legat (ACM Trans. Reconfigurable Technol. Syst., 2012)

An efficient metric of setup time for pulsed flip-flops based on output transition time. - Sebastien Bernard; Alexandre Valentian; Marc Belleville; David Bol; Jean-Didier Legat (ICICDT, 2013)

SleepWalker: A 25-MHz 0.4-V Sub-mm2 7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes. - David Bol; Julien De Vos; Cédric Hocquet; François Botman; François Durvaux; Sarah Boyd; Denis Flandre; Jean-Didier Legat (IEEE J. Solid State Circuits, 2013)

Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes. - François Botman; Julien De Vos; Sebastien Bernard; François Stas; Jean-Didier Legat; David Bol (ISCAS, 2014)

Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. - Sebastien Bernard; Marc Belleville; Alexandre Valentian; Jean-Didier Legat; David Bol (PATMOS, 2014)

A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations. - Sebastien Bernard; Alexandre Valentian; David Bol; Jean-Didier Legat; Marc Belleville (J. Low Power Electron., 2014)

Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits. - François Botman; David Bol; Jean-Didier Legat; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications. - Charlotte Frenkel; Jean-Didier Legat; David Bol (ReCoSoC, 2015)

Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications. - Charlotte Frenkel; Jean-Didier Legat; David Bol (VLSI-SoC, 2016)

Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI. - Sebastien Bernard; Marc Belleville; Jean-Didier Legat; Alexandre Valentian; David Bol (Microelectron. J., 2016)

A compact phenomenological digital neuron implementing the 20 Izhikevich behaviors. - Charlotte Frenkel; Jean-Didier Legat; David Bol (BioCAS, 2017)

A fully-synthesized 20-gate digital spike-based synapse with embedded online learning. - Charlotte Frenkel; Giacomo Indiveri; Jean-Didier Legat; David Bol (ISCAS, 2017)

A 0.086-mm2 9.8-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS. - Charlotte Frenkel; Jean-Didier Legat; David Bol (CoRR, 2018)

A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning. - Charlotte Frenkel; Jean-Didier Legat; David Bol (ISCAS, 2019)

MorphIC: A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning. - Charlotte Frenkel; Jean-Didier Legat; David Bol (IEEE Trans. Biomed. Circuits Syst., 2019)

A 0.086-mm2 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS. - Charlotte Frenkel; Martin Lefebvre 002; Jean-Didier Legat; David Bol (IEEE Trans. Biomed. Circuits Syst., 2019)

A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas. - Charlotte Frenkel; Jean-Didier Legat; David Bol (ISCAS, 2020)