Preform: A Process Independent Symbolic Layout System. - Jean-Claude Dufourd; Jean-François Naviner; Francis Jutand (ICCAD, 1990)

Préforme/aGAPE: a synergy between symbolic cell design and assembly. - Jean-François Naviner; Jean-Claude Dufourd (Microprocess. Microprogramming, 1993)

An Optimizable Model for Process Independent Symbolic Design. - Jean-Claude Dufourd; Jean-François Naviner (EDAC-ETC-EUROASIC, 1994)

A track&hold-mixer for direct-conversion by subsampling. - T. Vasseaux; B. Huyart; Patrick Loumeau; Jean-François Naviner (ISCAS (4), 1999)

Antialiasing filtering influences on ADC specifications for radio receivers. - Elizabeth Colin; Patrick Loumeau; Lirida A. B. Naviner; Jean-François Naviner (ICECS, 2001)

A switched-current sample and hold circuit for low frequency applications. - Elizabeth de Lira Mendes; Patrick Loumeau; Jean-François Naviner (ISCAS (1), 2001)

Trade-off between antialiasing filter and analog-to-digital converters specifications in homodyne radio frequency receivers. - Elizabeth Colin; Lirida A. B. Naviner; Patrick Loumeau; Jean-François Naviner (VTC Fall, 2001)

An interleaved delta-sigma analog to digital converter with digital correction. - Van Tam Nguyen 001; Patrick Loumeau; Jean-François Naviner (ICASSP, 2002)

A time-interleaved chopper-stabilized delta-sigma analog to digital converter. - Van Tam Nguyen 001; Patrick Loumeau; Jean-François Naviner (ICECS, 2002)

Analysis of time-interleaved delta-sigma analog to digital converter. - Van Tam Nguyen 001; Patrick Loumeau; Jean-François Naviner (VTC Spring, 2002)

Analog to digital conversion: technical aspects. - Patrick Loumeau; Jean-François Naviner; Hervé Petit; Lirida A. B. Naviner; Patricia Desgreys (Ann. des Télécommunications, 2002)

Temporel and spectral analysis of time interleaved high pass sigma delta converter. - Van-Tam Nguyen 001; Patrick Loumeau; Jean-François Naviner (ICASSP (2), 2003)

Designing a programmable analog signal conditioning circuit without loss of measurement range. - Sebastian Yuri Cavalcanti Catunda; Jean-François Naviner; Gurdip Singh Deep; Raimundo Carlos Silvério Freire (IEEE Trans. Instrum. Meas., 2003)

Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters. - David Camarero; Jean-François Naviner; Patrick Loumeau (SBCCI, 2004)

Systems-on-chip for telecommunications. - Jean-François Naviner; Amara Amara (Ann. des Télécommunications, 2004)

Calibration of sampling instants in a multiple channel time-interleaved analog-to-digital converter. - David Camarero; Jean-François Naviner; Patrick Loumeau (ICECS, 2005)

Impact of charge injection on system-level performance of a discrete-time GSM receiver. - Rayan Mina; Jean-Charles Grasset; Jean-François Naviner (ICECS, 2006)

High-pass Delta Sigma modulator: from system analysis to circuit design. - Van Tam Nguyen 001; Patrick Loumeau; Jean-François Naviner (ISCAS, 2006)

A CMOS implementation of time-interleaved high-pass Delta Sigma modulator. - Van Tam Nguyen 001; Patrick Loumeau; Jean-François Naviner (ISCAS, 2006)

Yield and reliability issues in nanoelectronic technologies. - Denis Teixeira Franco; Jean-François Naviner; Lirida A. B. Naviner (Ann. des Télécommunications, 2006)

Methods and Metrics for Reliability Assessment. - Lirida Alves de Barros Naviner; Jean-François Naviner; Denis Teixeira Franco; Maí Correia R. de Vasconcelos (Fault-Tolerant Distributed Algorithms on VLSI Chips, 2008)

Reliability analysis of logic circuits based on signal probability. - Denis Teixeira Franco; Maí Correia Vasconcelos; Lirida A. B. Naviner; Jean-François Naviner (ICECS, 2008)

On the output events in concurrent error detection schemes. - Maí Correia R. de Vasconcelos; Denis Teixeira Franco; Lirida A. B. Naviner; Jean-François Naviner (ICECS, 2008)

A Novel Approach to Non Coherent UWB Reception. - Aamir Riaz; Jean-François Naviner; Van Tam Nguyen 004 (IMTIC, 2008)

Signal probability for reliability evaluation of logic circuits. - Denis Teixeira Franco; Maí Correia Vasconcelos; Lirida A. B. Naviner; Jean-François Naviner (Microelectron. Reliab., 2008)

Relevant metrics for evaluation of concurrent error detection schemes. - Maí Correia R. de Vasconcelos; Denis Teixeira Franco; Lirida A. B. Naviner; Jean-François Naviner (Microelectron. Reliab., 2008)

Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs. - David Camarero; Karim Ben Kalaia; Jean-François Naviner; Patrick Loumeau (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

AMS and RF design for reliability methodology. - Pietro Maris Ferreira; Hervé Petit; Jean-François Naviner (ISCAS, 2010)

On evaluating the signal reliability of self-checking arithmetic circuits. - Denis Teixeira Franco; Maí Correia Vasconcelos; Lirida A. B. Naviner; Jean-François Naviner (SBCCI, 2010)

An efficient tool for reliability improvement based on TMR. - Elaine Crespo Marques; Lirida A. B. Naviner; Jean-François Naviner (Microelectron. Reliab., 2010)

Using error tolerance of target application for efficient reliability improvement of digital circuits. - G. G. dos Santos; Elaine Crespo Marques; Lirida A. B. Naviner; Jean-François Naviner (Microelectron. Reliab., 2010)

A new synthesis methodology for reliable RF front-end Design. - Pietro Maris Ferreira; Hervé Petit; Jean-François Naviner (ISCAS, 2011)

Reliability aware design of low power continuous-time sigma-delta modulator. - Hao Cai 001; Hervé Petit; Jean-François Naviner (Microelectron. Reliab., 2011)

A synthesis methodology for AMS/RF circuit reliability: Application to a DCO design. - Pietro Maris Ferreira; Hervé Petit; Jean-François Naviner (Microelectron. Reliab., 2011)

FIFA: A fault-injection-fault-analysis-based tool for reliability assessment at RTL level. - Lirida A. B. Naviner; Jean-François Naviner; G. G. dos Santos Jr.; Elaine Crespo Marques; Nilson M. Paiva Jr. (Microelectron. Reliab., 2011)

Automatic selective hardening against soft errors: A cost-based and regularity-aware approach. - Samuel N. Pagliarini; Arwa Ben Dhia; Lirida Alves de Barros Naviner; Jean-François Naviner (ICECS, 2012)

Selective hardening methodology for combinational logic. - Samuel Nascimento Pagliarini; Lirida A. B. Naviner; Jean-François Naviner (LATW, 2012)

Reliability analysis of a Reed-Solomon decoder. - Kaikai Liu; Tian Ban; Lirida A. B. Naviner; Jean-François Naviner (MWSCAS, 2012)

A Hierarchical Reliability Simulation Methodology for AMS Integrated Circuits and Systems. - Hao Cai 001; Hervé Petit; Jean-François Naviner (J. Low Power Electron., 2012)

Exploring the feasibility of selective hardening for combinational logic. - Samuel N. Pagliarini; G. G. dos Santos; Lirida Alves de Barros Naviner; Jean-François Naviner (Microelectron. Reliab., 2012)

Reliability analysis of combinational circuits with the influences of noise and single-event transients. - Kaikai Liu; Hao Cai 001; Ting An; Lirida A. B. Naviner; Jean-François Naviner; Hervé Petit (DFTS, 2013)

A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology. - Kaikai Liu; Ting An; Hao Cai 001; Lirida A. B. Naviner; Jean-François Naviner; Hervé Petit (EUROCON, 2013)

Single event transient mitigation through pulse quenching: Effectiveness at circuit level. - Samuel N. Pagliarini; Lirida A. B. Naviner; Jean-François Naviner (ICECS, 2013)

Reliability assessment of combinational logic using first-order-only fanout reconvergence analysis. - Samuel N. Pagliarini; Tian Ban; Lirida A. B. Naviner; Jean-François Naviner (MWSCAS, 2013)

A fast reliability-aware approach for analogue integrated circuits based on Pareto fronts. - Hao Cai 001; Hervé Petit; Jean-François Naviner (NEWCAS, 2013)

Selective hardening against multiple faults employing a net-based reliability analysis. - Samuel N. Pagliarini; Lirida A. B. Naviner; Jean-François Naviner (NEWCAS, 2013)

SNaP: A novel hybrid method for circuit reliability assessment under multiple faults. - Samuel N. Pagliarini; Arwa Ben Dhia; Lirida Alves de Barros Naviner; Jean-François Naviner (Microelectron. Reliab., 2013)

Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. - Lirida A. B. Naviner; Kaikai Liu; Hao Cai 001; Jean-François Naviner (ICICDT, 2014)

A hybrid reliability assessment method and its support of sequential logic modelling. - Samuel N. Pagliarini; Lirida A. B. Naviner; Jean-François Naviner; Dhiraj K. Pradhan (IOLTS, 2014)

Cross-layer investigation of continuous-time sigma-delta modulator under aging effects. - Hao Cai 001; You Wang 002; Kaikai Liu; Lirida Alves de Barros Naviner; Hervé Petit; Jean-François Naviner (Microelectron. Reliab., 2015)

Efficient reliability evaluation methodologies for combinational circuits. - Hao Cai 001; Kaikai Liu; Lirida Alves de Barros Naviner; You Wang 002; Mariem Slimani; Jean-François Naviner (Microelectron. Reliab., 2016)