Mathematical model for simulation of hierarchically distributed process control computer systems. - Jacob Davidson; Jean-Louis Houle (Autom., 1988)

Impact of reconfiguration logic on the optimization of defect-tolerant integrated circuits. - Claude Thibeault; Jean-Louis Houle (FTCS, 1990)

Test quality of hierarchical defect-tolerant integrated circuits. - Claude Thibeault; Yvon Savaria; Jean-Louis Houle (J. Electron. Test., 1992)

Heuristic Prediction of the Optimum Number of spares in Defect-Tolerant Integrated Circuits. - Claude Thibeault; Yvon Savaria; Jean-Louis Houle (J. Circuits Syst. Comput., 1992)

Performance improvements to VLSI parallel systems, using dynamic concatenation of processing resources. - Daniel Audet; Yvon Savaria; Jean-Louis Houle (Parallel Comput., 1992)

A High Speed Parallel Structure for the Basic Wavelet Transform Algorithm. - Hakim Khali; Jean-Louis Houle; Yvon Savaria (ISCAS, 1993)

FPGA Implementation of Wavelet Transforms. - Chokri Achour; Jacob Davidson; Jean-Louis Houle (Applied Informatics, 1994)

A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits. - Claude Thibeault; Yvon Savaria; Jean-Louis Houle (IEEE Trans. Computers, 1994)

Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits. - Claude Thibeault; Yvon Savaria; Jean-Louis Houle (IEEE Trans. Computers, 1995)

A Geomatic System for Real-Time Applications. - Natalie Pronovost; Jean-Louis Houle (Applied Informatics, 1999)

A VLSI architecture of 2D wavelet transforms. - Chokri Achour; Jean-Louis Houle; Jacob Davidson (ICECS, 2000)

Improvement of sensor accuracy in the case of a variable surface reflectance gradient for active laser range finders. - Hakim Khali; Yvon Savaria; Jean-Louis Houle; Marc Rioux; J.-Angelo Beraldin; D. Poussart (IEEE Trans. Instrum. Meas., 2003)

A system level implementation strategy and partitioning heuristic for LUT-based applications. - Hakim Khali; Yvon Savaria; Jean-Louis Houle (Comput. Electr. Eng., 2005)