The Database Processor 'RAPID'. - Pascal Faudemay; Daniel Etiemble; Jean-Luc Béchennec; He Hé (IWDM, 1987)

A highly parallel processor with an instruction set including relational algebra. - Pascal Faudemay; Daniel Etiemble; Jean-Luc Béchennec (ICCD, 1988)

A risc central processing unit for a massivelly parallel architecture. - Franck Cappello; Jean-Luc Béchennec; Daniel Etiemble (Microprocessing and Microprogramming, 1990)

3D hardware packages for parallel architectures. - Jean-Luc Béchennec; Franck Cappello; Daniel Etiemble (Microprocessing and Microprogramming, 1991)

PTAH: Introduction to a New Parallel Architecture for Highly Numeric Processing. - Franck Cappello; Jean-Luc Béchennec; Jean-Louis Giavitto (PARLE, 1992)

Design of the processing node of the PTAH 64 parallel computer. - Franck Cappello; Jean-Luc Béchennec; J.-L. Glavitto (Microprocess. Microprogramming, 1992)

Balanced Distributed Memory Parallel Computers. - Franck Cappello; Jean-Luc Béchennec; Franck Delaplace; Cécile Germain; Jean-Louis Giavitto; Vincent Néri; Daniel Etiemble (ICPP (1), 1993)

A Parralel Architecture Based on Compiled Communication Schemes. - Franck Cappello; Jean-Luc Béchennec; Franck Delaplace; Damien Gautier de Lahaut; Cécile Germain; Jean-Louis Giavitto; Vincent Néri; Daniel Etiemble (PARCO, 1993)

Static computation of standard linear algebra subroutines for PTAH. - E. Daugeras; Jean-Luc Béchennec; Franck Cappello (PDP, 1993)

A Communication Architecture for a Massively Parallel Message-Passing Multicomputer. - Cécile Germain; Jean-Luc Béchennec; Daniel Etiemble; Jean-Paul Sansonnet (J. Parallel Distributed Comput., 1993)

Hardware features of the static communication network of a parallel architecture. - Vincent Néri; Jean-Luc Béchennec; Franck Cappello; Daniel Etiemble (Microprocess. Microprogramming, 1993)

Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces. - A. Pavlov; Jean-Luc Béchennec; Daniel Etiemble (EUROMICRO, 1997)

Evaluation of High Performance Multicache Parallel Texture Mapping. - Alexis Vartanian; Jean-Luc Béchennec; Nathalie Drach-Temam (International Conference on Supercomputing, 1998)

ASF: a teaching and rsearch object-oriented simulation tool for computer architecture design and performance evaluation. - Jean-Luc Béchennec (WCAE@ISCA, 1998)

A Parallel Algorithm for 3D Geometry Transformations in OpenGL. - Julien Sébot; Alexis Vartanian; Jean-Luc Béchennec; Nathalie Drach-Temam (Euro-Par, 1999)

PopSPY: A PowerPC Instrumentation Tool for Multiprocessor Simulation. - Claude Limousin; Alexis Vartanian; Jean-Luc Béchennec (Euro-Par, 1999)

Two Schemes to Improve the Performance of a Sort-Last 3D Parallel Rendering Machine with Texture Caches. - Alexis Vartanian; Jean-Luc Béchennec; Nathalie Drach-Temam (Euro-Par, 1999)

The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches. - Alexis Vartanian; Jean-Luc Béchennec; Nathalie Drach-Temam (HPCA, 2000)

Increasing hardware data prefetching performance using the second-level cache. - Nathalie Drach; Jean-Luc Béchennec; Olivier Temam (J. Syst. Archit., 2002)

Trampoline An Open Source Implementation of the OSEK/VDX RTOS Specification. - Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Yvon Trinquet (ETFA, 2006)

Simulator generation using an automaton based pipeline model for timing analysis. - Rola Kassem; Mikaël Briday; Jean-Luc Béchennec; Yvon Trinquet; Guillaume Savaton (IMCSIT, 2008)

Instruction set simulator generation using HARMLESS, a new hardware architecture description language. - Rola Kassem; Mikaël Briday; Jean-Luc Béchennec; Yvon Trinquet; Guillaume Savaton (SimuTools, 2009)

ViPER: a lightweight approach to the simulation of distributed and embedded software. - Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Florent Pavin; Fabien Juif (SimuTools, 2010)

Extending Harmless architecture description language for embedded real-time systems validation. - Jean-Luc Béchennec; Mikaël Briday; Valere Alibert (SIES, 2011)

Computation of WCET using Program Slicing and Real-Time Model-Checking - Jean-Luc Béchennec; Franck Cassez (CoRR, 2011)

An Architecture Description Language for Embedded Hardware Platforms. - Guillaume Savaton; Jean-Luc Béchennec; Mikaël Briday; Rola Kassem (Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2011)

A Data Flow Monitoring Service Based on Runtime Verification for AUTOSAR. - Sylvain Cotard; Sébastien Faucou; Jean-Luc Béchennec; Audrey Queudet; Yvon Trinquet (HPCC-ICESS, 2012)

Harmless, a hardware architecture description language dedicated to real-time embedded system simulation. - Rola Kassem; Mikaël Briday; Jean-Luc Béchennec; Guillaume Savaton; Yvon Trinquet (J. Syst. Archit., 2012)

Timing Analysis of Binary Programs with UPPAAL. - Franck Cassez; Jean-Luc Béchennec (ACSD, 2013)

Device driver synthesis for embedded systems. - Julien Tanguy; Jean-Luc Béchennec; Mikaël Briday; Sebastien Dube; Olivier H. Roux (ETFA, 2013)

Reactive embedded device driver synthesis using logical timed models. - Julien Tanguy; Jean-Luc Béchennec; Mikaël Briday; Olivier H. Roux (SIMULTECH, 2014)

Improving processor hardware compiled cycle accurate simulation using program abstraction. - Adrien Bullich; Mikaël Briday; Jean-Luc Béchennec; Yvon Trinquet (SimuTools, 2014)

Formal Synthesis of Optimal RTOS. - Tigori Kabland Toussaint Gautier; Jean-Luc Béchennec; Olivier Henry Roux (HPCC/CSS/ICESS, 2015)

STM-HRT: A Robust and Wait-Free STM for Hard Real-Time Multicore Embedded Systems. - Sylvain Cotard; Audrey Queudet; Jean-Luc Béchennec; Sébastien Faucou; Yvon Trinquet (ACM Trans. Embed. Comput. Syst., 2015)

Testing real-time embedded software using runtime enforcement. - Louis-Marie Givel; Jean-Luc Béchennec; Matthias Brun 001; Sébastien Faucou; Olivier H. Roux (SIES, 2016)

Hardware runtime verification of embedded software in SoPC. - Dimitry Solet; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Sébastien Pillement (SIES, 2016)

BEST: a Binary Executable Slicing Tool. - Armel Mangean; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou (WCET, 2016)

WCET Analysis by Model Checking for a Processor with Dynamic Branch Prediction. - Armel Mangean; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou (VECoS, 2017)

Formal Model-Based Synthesis of Application-Specific Static RTOS. - Tigori Kabland Toussaint Gautier; Jean-Luc Béchennec; Sébastien Faucou; Olivier Henry Roux (ACM Trans. Embed. Comput. Syst., 2017)

HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems. - Dimitry Solet; Jean-Luc Béchennec; Mikaël Briday (AHS, 2018)

Formal model-based conformance verification of an OSEK/VDX compliant RTOS. - Jean-Luc Béchennec; Olivier Henry Roux; Tigori Kabland Toussaint Gautier (CoDIT, 2018)

Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection. - Dimitry Solet; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Sébastien Pillement (EDCC, 2018)

Formal approach for a verified implementation of Global EDF in Trampoline. - Khaoula Boukir; Jean-Luc Béchennec; Anne-Marie Déplanche (RTNS, 2018)

Testing Real-Time Systems With Runtime Enforcement. - Jean-Luc Béchennec; Sébastien Faucou; Olivier H. Roux; Matthias Brun 001; Louis-Marie Givel (IEEE Des. Test, 2018)

Control of DES with Urgency, Avoidability and Ineluctability. - Jean-Luc Béchennec; Didier Lime; Olivier H. Roux (ACSD, 2019)

Requirement specification and model-checking of a real-time scheduler implementation. - Khaoula Boukir; Jean-Luc Béchennec; Anne-Marie Déplanche (RTNS, 2020)

Energy Efficiency is Not Enough: Towards a Batteryless Internet of Sounds. - Vincent Lostanlen; Antoine Bernabeu; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Mathieu Lagrange (Audio Mostly Conference, 2021)

Formal schedulability analysis based on multi-core RTOS model. - Imane Haur; Jean-Luc Béchennec; Olivier Henri Roux (RTNS, 2021)

Logical time control of concurrent DES. - Jean-Luc Béchennec; Didier Lime; Olivier H. Roux (Discret. Event Dyn. Syst., 2021)

High-level Colored Time Petri Nets for true concurrency modeling in real-time software. - Imane Haur; Jean-Luc Béchennec; Olivier H. Roux (CoDIT, 2022)

Formal Verification of the Inter-core Synchronization of a Multi-core RTOS Kernel. - Imane Haur; Jean-Luc Béchennec; Olivier H. Roux (ICFEM, 2022)

Securing a RISC-V architecture: A dynamic approach. - Sébastien Pillement; Maria Mendez Real; J. Pottier; T. Nieddu; Bertrand Le Gal; Sébastien Faucou; Jean-Luc Béchennec; Mikaël Briday; Sylvain Girbal; Jimmy Le Rhun; Olivier Gilles; Daniel Gracia Pérez; et al. (DATE, 2023)

Cost-optimal timed trace synthesis for scheduling of intermittent embedded systems. - Antoine Bernabeu; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Olivier H. Roux (Discret. Event Dyn. Syst., 2023)

Formal verification process of the compliance of a multicore AUTOSAR OS. - Imane Haur; Jean-Luc Béchennec; Olivier H. Roux (Softw. Qual. J., 2023)

SCHEMATIC: Compile-Time Checkpoint Placement and Memory Allocation for Intermittent Systems. - Hugo Reymond; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Isabelle Puaut; Erven Rohou (CGO, 2024)

EarlyBird: Energy belongs to those who wake up early. - Hugo Reymond; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Isabelle Puaut; Erven Rohou (RTCSA, 2024)

Verifying Timed Properties of Programs in IoT nodes using Parametric Time Petri Nets. - Étienne André; Jean-Luc Béchennec; Sudipta Chattopadhyay 001; Sébastien Faucou; Didier Lime; Dylan Marinho; Olivier H. Roux; Jun Sun 001 (SAC, 2025)

A Study in Specification and Hardware Runtime Verification of Critical Embedded Software. - Dimitry Solet; Jean-Luc Béchennec; Mikaël Briday; Sébastien Faucou; Sébastien Pillement (IEEE Trans. Dependable Secur. Comput., 2025)

Model-Checking of Concurrent Real-Time Software Using High-Level Colored Time Petri Nets with Stopwatches. - Imane Haur; Jean-Luc Béchennec; Olivier H. Roux (Cybern. Syst., 2025)