RENCO: A Reconfigurable Network Computer. - Jacques-Olivier Haenni; Jean-Luc Beuchat; Eduardo Sanchez (FCCM, 1998)

Hardware Reconfigurable Neural Networks. - Jean-Luc Beuchat; Jacques-Olivier Haenni; Eduardo Sanchez (IPPS/SPDP Workshops, 1998)

An On-Line Arithmetic-Based Reconfigurable Neuroprocessor. - Jean-Luc Beuchat; Eduardo Sanchez (IPPS/SPDP Workshops, 1999)

Using On-Line Arithmetic and Reconfiguration for Neuroprocessor Implementations. - Jean-Luc Beuchat; Eduardo Sanchez (IWANN (2), 1999)

Static and Dynamic Configurable Systems. - Eduardo Sanchez; Moshe Sipper; Jacques-Olivier Haenni; Jean-Luc Beuchat; André Stauffer; Andrés Pérez-Uribe (IEEE Trans. Computers, 1999)

Von Neumann's 29-state cellular automaton: a hardware implementation. - Jean-Luc Beuchat; Jacques-Olivier Haenni (IEEE Trans. Educ., 2000)

Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices. - Jean-Luc Beuchat; Arnaud Tisserand (FPL, 2002)

Approches matérielles et logicielles de l'algorithme de chiffrement IDEA. - Jean-Luc Beuchat; Jacques-Olivier Haenni; Héctor Fabio Restrepo; Christof Teuscher; Francisco J. Gómez; Eduardo Sanchez (Tech. Sci. Informatiques, 2002)

Modular Multiplication for FPGA Implementation of the IDEA Block Cipher. - Jean-Luc Beuchat (ASAP, 2003)

FPGA Implementations of the RC6 Block Cipher. - Jean-Luc Beuchat (FPL, 2003)

Some Modular Adders and Multipliers for Field Programmable Gate Arrays. - Jean-Luc Beuchat (IPDPS, 2003)

Évaluation polynomiale en-ligne de fonctions élémentaires sur FPGA. - Jean-Luc Beuchat; Arnaud Tisserand (Tech. Sci. Informatiques, 2004)

Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement. - Jean-Luc Beuchat; Jean-Michel Muller (ASAP, 2005)

An Algorithm for the ηT Pairing Calculation in Characteristic Three and its Hardware Implementation. - Jean-Luc Beuchat; Masaaki Shirase; Tsuyoshi Takagi; Eiji Okamoto (IACR Cryptol. ePrint Arch., 2006)

Multiplication over Fpm on FPGA: A Survey. - Jean-Luc Beuchat; Takanori Miyoshi; Yoshihito Oyama; Eiji Okamoto (ARC, 2007)

An Algorithm for the nt Pairing Calculation in Characteristic Three and its Hardware Implementation. - Jean-Luc Beuchat; Masaaki Shirase; Tsuyoshi Takagi; Eiji Okamoto (IEEE Symposium on Computer Arithmetic, 2007)

A Coprocessor for the Final Exponentiation of the eta T Pairing in Characteristic Three. - Jean-Luc Beuchat; Nicolas Brisebarre; Masaaki Shirase; Tsuyoshi Takagi; Eiji Okamoto (WAIFI, 2007)

Further Comments on "Residue-to-Binary Converters Based on New Chinese Remainder Theorems" - Jean-Luc Beuchat (CoRR, 2007)

Arithmetic Operators for Pairing-Based Cryptography. - Jean-Luc Beuchat; Nicolas Brisebarre; Jérémie Detrey; Eiji Okamoto (IACR Cryptol. ePrint Arch., 2007)

Algorithms and Arithmetic Operators for Computing the etaT Pairing in Characteristic Three. - Jean-Luc Beuchat; Nicolas Brisebarre; Jérémie Detrey; Eiji Okamoto; Masaaki Shirase; Tsuyoshi Takagi (IACR Cryptol. ePrint Arch., 2007)

A Coprocessor for the Final Exponentiation of the etaT Pairing in Characteristic Three. - Jean-Luc Beuchat; Nicolas Brisebarre; Masaaki Shirase; Tsuyoshi Takagi; Eiji Okamoto (IACR Cryptol. ePrint Arch., 2007)

A Refined Algorithm for the etaT Pairing Calculation in Characteristic Three. - Jean-Luc Beuchat; Masaaki Shirase; Tsuyoshi Takagi; Eiji Okamoto (IACR Cryptol. ePrint Arch., 2007)

A Comparison Between Hardware Accelerators for the Modified Tate Pairing over F2m and F3m. - Jean-Luc Beuchat; Nicolas Brisebarre; Jérémie Detrey; Eiji Okamoto; Francisco Rodríguez-Henríquez (IACR Cryptol. ePrint Arch., 2008)

A Pipelined Karatsuba-Ofman Multiplier over GF(397) Amenable for Pairing Computation. - Nidia Cortez-Duarte; Francisco Rodríguez-Henríquez; Jean-Luc Beuchat; Eiji Okamoto (IACR Cryptol. ePrint Arch., 2008)

Algorithms and Arithmetic Operators for Computing the etaT Pairing in Characteristic Three. - Jean-Luc Beuchat; Nicolas Brisebarre; Jérémie Detrey; Eiji Okamoto; Masaaki Shirase; Tsuyoshi Takagi (IEEE Trans. Computers, 2008)

Automatic Generation of Modular Multipliers for FPGA Applications. - Jean-Luc Beuchat; Jean-Michel Muller (IEEE Trans. Computers, 2008)

Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers. - Jean-Luc Beuchat; Jérémie Detrey; Nicolas Estibals; Eiji Okamoto; Francisco Rodríguez-Henríquez (IACR Cryptol. ePrint Arch., 2009)

Fast Architectures for the etaT Pairing over Small-Characteristic Supersingular Elliptic Curves. - Jean-Luc Beuchat; Jérémie Detrey; Nicolas Estibals; Eiji Okamoto; Francisco Rodríguez-Henríquez (IACR Cryptol. ePrint Arch., 2009)

Multi-core Implementation of the Tate Pairing over Supersingular Elliptic Curves. - Jean-Luc Beuchat; Emmanuel López-Trejo; Luis Martínez-Ramos; Shigeo Mitsunari; Francisco Rodríguez-Henríquez (IACR Cryptol. ePrint Arch., 2009)

FPGA and ASIC implementations of the etaT pairing in characteristic three. - Jean-Luc Beuchat; Hiroshi Doi; Kaoru Fujita; Atsuo Inomata; Piseth Ith; Akira Kanaoka; Masayoshi Katouno; Masahiro Mambo; Eiji Okamoto; Takeshi Okamoto; Takaaki Shiga; Masaaki Shirase; et al. (Comput. Electr. Eng., 2010)

Optimal Eta Pairing on Supersingular Genus-2 Binary Hyperelliptic Curves. - Diego F. Aranha; Jean-Luc Beuchat; Jérémie Detrey; Nicolas Estibals (IACR Cryptol. ePrint Arch., 2010)

High-Speed Software Implementation of the Optimal Ate Pairing over Barreto-Naehrig Curves. - Jean-Luc Beuchat; Jorge Enrique González-Díaz; Shigeo Mitsunari; Eiji Okamoto; Francisco Rodríguez-Henríquez; Tadanori Teruya (IACR Cryptol. ePrint Arch., 2010)

Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA. - Jean-Luc Beuchat; Eiji Okamoto; Teppei Yamazaki (IACR Cryptol. ePrint Arch., 2010)

A Compact FPGA Implementation of the SHA-3 Candidate ECHO. - Jean-Luc Beuchat; Eiji Okamoto; Teppei Yamazaki (IACR Cryptol. ePrint Arch., 2010)

A low-area unified hardware architecture for the AES and the cryptographic hash function ECHO. - Jean-Luc Beuchat; Eiji Okamoto; Teppei Yamazaki (J. Cryptogr. Eng., 2011)

Fast Architectures for the eta_T Pairing over Small-Characteristic Supersingular Elliptic Curves. - Jean-Luc Beuchat; Jérémie Detrey; Nicolas Estibals; Eiji Okamoto; Francisco Rodríguez-Henríquez (IEEE Trans. Computers, 2011)

Compact Implementation of Threefish and Skein on FPGA. - Nuray At; Jean-Luc Beuchat; Ismail San (IACR Cryptol. ePrint Arch., 2012)

Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA. - Nuray At; Jean-Luc Beuchat; Eiji Okamoto; Ismail San; Teppei Yamazaki (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Guest Editorial: Introduction to the Special Section on Emerging Security Trends for Biomedical Computations, Devices, and Infrastructures. - Mehran Mozaffari Kermani; Reza Azarderakhsh; Kui Ren 001; Jean-Luc Beuchat (IEEE ACM Trans. Comput. Biol. Bioinform., 2016)

A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl. - Nuray At; Jean-Luc Beuchat; Eiji Okamoto; Ismail San; Teppei Yamazaki (J. Parallel Distributed Comput., 2017)

A Digital Identity in the Hands of Swiss Citizens. - Jean-Luc Beuchat; Valon Rexhepi (IACR Cryptol. ePrint Arch., 2023)