Vector addressing processor for direct and indirect accesses. - Jean-Luc Dekeyser; Philippe Marquet; Philippe Preux (Microprocessing and Microprogramming, 1990)

EVA: an explicit vector language. - Jean-Luc Dekeyser; Philippe Marquet; Philippe Preux (ACM SIGPLAN Notices, 1990)

Performance improvement for vector pipeline multiprocessor systems using a disordered execution model. - M. Tahar Kechadi; Jean-Luc Dekeyser; Philippe Marquet; Philippe Preux (ISCA, 1992)

HelpDraw Graphical Environment: A Step Beyond Data Parallel Programming Languages. - Akram-Djellal Benalia; Jean-Luc Dekeyser; Philippe Marquet (HCI (2), 1993)

Dynamic Load Balancing on SIMD Data-Parallel Computers. - Cyril Fonlupt; Jean-Luc Dekeyser; Philippe Marquet (EUROSIM, 1994)

A Data-Parallel View of the Load Balancing - Experimental Results on MasPar MP-1. - Cyril Fonlupt; Philippe Marquet; Jean-Luc Dekeyser (HPCN, 1994)

A Geometrical Data-Parallel Language. - Jean-Luc Dekeyser; Dominique Lazure; Philippe Marquet (ACM SIGPLAN Notices, 1994)

Analysis of Synchronous Dynamic Load Balancing Algorithms. - Cyril Fonlupt; Philippe Marquet; Jean-Luc Dekeyser (PARCO, 1995)

Supporting Irregular and Dynamic Computations in Data Parallel Languages. - Jean-Luc Dekeyser; Philippe Marquet (The Data Parallel Programming Model, 1996)

Dynamic Redistribution on Heterogeneous Parallel Computers. - Dominique Sueur; Jean-Luc Dekeyser (Euro-Par, Vol. I, 1996)

Mixed synchronous-asynchronous approach for real-time image processing: a MPEG-like coder. - David Galinec; Jean-Luc Dekeyser; Philippe Marquet (ICIP (2), 1996)

Irregular Data-Parallel Objects in C++. - Jean-Luc Dekeyser; Boris Kokoszko; Jean-Luc Levaire; Philippe Marquet (VECPAR, 1996)

Step By Step Transformation of a Fortran 90 Program in HPF, using HPF-Builder. - Jean-Luc Dekeyser; Christian Lefebvre (PP, 1997)

Data Parallel File System. - Jean-Luc Dekeyser; Dominique Sueur (PP, 1997)

Hpf-Builder: a Visual Environment To Transform Fortran 90 Codes To Hpf. - Jean-Luc Dekeyser; Christian Lefebvre (Int. J. High Perform. Comput. Appl., 1997)

Analysis and Simulation of an Out-Of-Order Execution Model in Vector Multiprocessor Systems. - M. Tahar Kechadi; Jean-Luc Dekeyser (Parallel Comput., 1997)

Implementation of a Bi-Parallel Monte Carlo Device Simulation on Two Architectures. - Fabien Banse; Jean-Luc Dekeyser; Renaud Fauquembergue; François Dessenne (HPCN Europe, 1998)

DPFS: A Data-Parallel File System Environment. - Dominique Sueur; Jean-Luc Dekeyser; Philippe Marquet (HPCN Europe, 1998)

Data-Parallel Load Balancing Strategies. - Cyril Fonlupt; Philippe Marquet; Jean-Luc Dekeyser (Parallel Comput., 1998)

Parallelization of a 3D Magnetostatic Code Using High Performance Fortran. - Emmanuel Cagniot; Jean-Luc Dekeyser; Pierre Boulet; Thomas Brandes; Francis Piriou; Georges Marques (PARELEC, 2000)

High Level Parallelization of a 3D Electromagnetic Simulation Code with Irregular Communication Patterns. - Emmanuel Cagniot; Thomas Brandes; Jean-Luc Dekeyser; Francis Piriou; Pierre Boulet; Stéphane Clénet (VECPAR, 2000)

Compilation Principle of a Specification Language Dedicated to Signal Processing. - Julien Soula; Philippe Marquet; Alain Demeure; Jean-Luc Dekeyser (PaCT, 2001)

Visual Data-Parallel Programming for Signal Processing Applications. - Pierre Boulet; Jean-Luc Dekeyser; Jean-Luc Levaire; Philippe Marquet; Julien Soula; Alain Demeure (PDP, 2001)

GASPARD - A Visual Parallel Programming Environment. - Florent Devin; Pierre Boulet; Jean-Luc Dekeyser; Philippe Marquet (PARELEC, 2002)

Towards Distributed Process Networks with CORBA. - Abdelkader Amar; Pierre Boulet; Jean-Luc Dekeyser (Parallel Distributed Comput. Pract., 2002)

An Interconnection Networks Comparative Performance Evaluation Methodology: Delta and Over-Sized Delta Networks. - Ahmad Chadi Aljundi; Jean-Luc Dekeyser; Isaac D. Scherson (PDCS, 2003)

MDA for SoC Design, Intensive Signal Processing Experiment. - Pierre Boulet; Jean-Luc Dekeyser; Cédric Dumoulin; Philippe Marquet (FDL, 2003)

Interoperability between Design and Simulation Tools using Model Transformation Techniques. - Cédric Dumoulin; Jean-Luc Dekeyser; Boris Kokoszko; S. Pulon; G. Cristau (FDL, 2003)

A Study of an Evaluation Methodology for Unbuffered Multistage Interconnection Networks. - Ahmad Chadi Aljundi; Jean-Luc Dekeyser; M. Tahar Kechadi; Isaac D. Scherson (IPDPS, 2003)

Distributed Process Networks - Using Half FIFO Queues in CORBA. - Abdelkader Amar; Pierre Boulet; Jean-Luc Dekeyser; T. Theeuwen (PARCO, 2003)

Metamodels and MDA Transformations for Embedded Systems. - Lossan Bonde; Cédric Dumoulin; Jean-Luc Dekeyser (FDL, 2004)

Regular Hardware Architecture Modeling with UML2. - Arnaud Cuccuru; Pierre Boulet; Jean-Luc Dekeyser (FDL, 2004)

MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing Applications. - M. Samyn; Samy Meftali; Jean-Luc Dekeyser (FDL, 2004)

An automatic communication synthesis for high level SOC desing using transaction level modelling (poster). - E. Turbatu; Samy Meftali; Smaïl Niar; Jean-Luc Dekeyser (FDL, 2004)

UML2 as an ADL Hierarchichal Hardware Modeling. - Arnaud Cuccuru; Philippe Marquet; Jean-Luc Dekeyser (IFIP-WADL, 2004)

SoCP2P: A Peer-to-Peer IPS Based SoC Design and Simulation Tool. - Samy Meftali; Jean-Luc Dekeyser (Virtual Enterprises and Collaborative Networks, 2004)

An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design. - Samy Meftali; Jean-Luc Dekeyser (IWSOC, 2004)

The Effect of the Degree of Multistage Interconnection Networks on their Performance: The Case of Delta and Over-Sized Delta Networks. - Ahmad Chadi Aljundi; Jean-Luc Dekeyser (PDP, 2004)

Traceability and Interoperability in Models Transformations. - Lossan Bonde; Pierre Boulet; Jean-Luc Dekeyser (FDL, 2005)

Embed Scripting inside SystemC. - J. Vennin; S. Penain; Luc Charest; Samy Meftali; Jean-Luc Dekeyser (FDL, 2005)

Mode-Automata Based Methodology for Scade. - Ouassila Labbani; Jean-Luc Dekeyser; Pierre Boulet (HSCC, 2005)

Scalable Multistage Network for Multiprocessor System-on-Chip Design. - Samy Meftali; Jean-Luc Dekeyser; Isaac D. Scherson (ISPAN, 2005)

Asymmetric Scheduling and Load Balancing for Real-Time on Linux SMP. - Éric Piel; Philippe Marquet; Julien Soula; Jean-Luc Dekeyser (PPAM, 2005)

Model Driven Engineering for Regular MPSoC Co-design. - Pierre Boulet; Arnaud Cuccuru; Jean-Luc Dekeyser; Ashish Meena (ReCoSoC, 2005)

Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies. - Arnaud Cuccuru; Jean-Luc Dekeyser; Philippe Marquet; Pierre Boulet (MoDELS, 2005)

Estimating Energy Consumption for an MPSoC Architectural Exploration. - Rabie Ben Atitallah; Smaïl Niar; Alain Greiner; Samy Meftali; Jean-Luc Dekeyser (ARCS, 2006)

FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar. - Sébastien Le Beux; Philippe Marquet; Ouassila Labbani; Jean-Luc Dekeyser (DSD, 2006)

UML2 Profile for Modeling Controlled Data Parallel Applications. - Ouassila Labbani; Éric Rutten; Jean-Luc Dekeyser; Pierre Boulet (FDL, 2006)

Real-time systems for multiprocessor architectures. - Éric Piel; Philippe Marquet; Julien Soula; Jean-Luc Dekeyser (IPDPS, 2006)

Multilevel MPSoC Performance Evaluation Using MDE Approach. - Rabie Ben Atitallah; Lossan Bonde; Smaïl Niar; Samy Meftali; Jean-Luc Dekeyser (SoC, 2006)

Safe Design Methodology for an Intelligent Cruise Control System with GPS. - Ouassila Labbani; Éric Rutten; Jean-Luc Dekeyser (VTC Fall, 2006)

A universal performance factor for multi-criteria evaluation of multistage interconnection networks. - Ahmad Chadi Aljundi; Jean-Luc Dekeyser; M. Tahar Kechadi; Isaac D. Scherson (Future Gener. Comput. Syst., 2006)

Massively parallel processing on a chip. - Philippe Marquet; Simon Duquennoy; Sébastien Le Beux; Samy Meftali; Jean-Luc Dekeyser (Conf. Computing Frontiers, 2007)

MARTE: UML-based Hardware Design from Modelling to Simulation. - Safouan Taha; Ansgar Radermacher; Sébastien Gérard; Jean-Luc Dekeyser (FDL, 2007)

Model Transformations from a Data Parallel Formalism towards Synchronous Languages. - Huafeng Yu; Abdoulaye Gamatié; Éric Rutten; Jean-Luc Dekeyser (FDL, 2007)

A Design Flow to Map Parallel Applications onto FPGAs. - Sébastien Le Beux; Philippe Marquet; Jean-Luc Dekeyser (FPL, 2007)

Model Transformations for the Compilation of Multi-processor Systems-on-Chip. - Éric Piel; Philippe Marquet; Jean-Luc Dekeyser (GTTSE, 2007)

Multiple Abstraction Views of FPGA to Map Parallel Applications. - Sébastien Le Beux; Philippe Marquet; Jean-Luc Dekeyser (ReCoSoC, 2007)

An MPSoC Performance Estimation Framework Using Transaction Level Modeling. - Rabie Ben Atitallah; Smaïl Niar; Samy Meftali; Jean-Luc Dekeyser (RTCSA, 2007)

An Open Framework for Detailed Hardware Modeling. - Safouan Taha; Ansgar Radermacher; Sebastien Gerard; Jean-Luc Dekeyser (SIES, 2007)

Multilevel MPSOC simulation using an MDE approach. - Rabie Ben Atitallah; Éric Piel; Smaïl Niar; Philippe Marquet; Jean-Luc Dekeyser (SoCC, 2007)

An MPSoC architecture for the Multiple Target Tracking application in driver assistant system. - Jehangir Khan; Smaïl Niar; Atika Rivenq; Yassin Elhillali; Jean-Luc Dekeyser (ASAP, 2008)

MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs. - Imran Rafiq Quadri; Samy Meftali; Jean-Luc Dekeyser (ESTIMedia, 2008)

MARTE-based Design of a Multimedia Application and Formal Analysis. - Adolf Samir Abdallah; Abdoulaye Gamatié; Jean-Luc Dekeyser (FDL, 2008)

Unifying HW Analysis and SoC Design Flows by Bridging Two Key Standards: UML and IP-XACT. - Sebastien Revol; Safouan Taha; François Terrier; Alain Clouard; Sébastien Gérard; Ansgar Radermacher; Jean-Luc Dekeyser (DIPES, 2008)

Using an MDE Approach for Modeling of Interconnection Networks. - Imran Rafiq Quadri; Pierre Boulet; Samy Meftali; Jean-Luc Dekeyser (ISPAN, 2008)

Modeling and Formal Validation of High-Performance Embedded Systems. - Abdoulaye Gamatié; Éric Rutten; Huafeng Yu; Pierre Boulet; Jean-Luc Dekeyser (ISPDC, 2008)

A Graphical Framework for High Performance Computing Using An MDE Approach. - Julien Taillard; Frédéric Guyomarc'h; Jean-Luc Dekeyser (PDP, 2008)

Synchronous Modeling and Analysis of Data Intensive Applications. - Abdoulaye Gamatié; Éric Rutten; Huafeng Yu; Pierre Boulet; Jean-Luc Dekeyser (EURASIP J. Embed. Syst., 2008)

Safe design of high-performance embedded systems in an MDE framework. - Huafeng Yu; Abdoulaye Gamatié; Éric Rutten; Jean-Luc Dekeyser (Innov. Syst. Softw. Eng., 2008)

Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA. - Mouna Baklouti; Mohamed Abid; Philippe Marquet; Jean-Luc Dekeyser (AICCSA, 2009)

Model-Driven Design of Embedded Multimedia Applications on SoCs. - Adolf Samir Abdallah; Abdoulaye Gamatié; Jean-Luc Dekeyser (DSD, 2009)

A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC. - Hajer Chtioui; Rabie Ben Atitallah; Smaïl Niar; Jean-Luc Dekeyser; Mohamed Abid (DSD, 2009)

A multi level functional verification of multistage interconnection network for MPSOC. - Yassine Aydi; Ramzi Tligue; Maissa Elleuch; Mohamed Abid; Jean-Luc Dekeyser (ICECS, 2009)

Traceability Mechanism for Error Localization in Model Transformation. - Vincent Aranega; Jean-Marie Mottu; Anne Etien; Jean-Luc Dekeyser (ICSOFT (1), 2009)

Using Trace to Situate Errors in Model Transformations. - Vincent Aranega; Jean-Marie Mottu; Anne Etien; Jean-Luc Dekeyser (ICSOFT (Selected Papers), 2009)

High level modeling of Dynamic Reconfigurable FPGAs. - Imran Rafiq Quadri; Samy Meftali; Jean-Luc Dekeyser (Int. J. Reconfigurable Comput., 2009)

Model-Driven Engineering and Formal Validation of High-Performance Embedded Systems. - Abdoulaye Gamatié; Éric Rutten; Huafeng Yu; Pierre Boulet; Jean-Luc Dekeyser (Scalable Comput. Pract. Exp., 2009)

Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip. - Mouna Baklouti; Philippe Marquet; Jean-Luc Dekeyser; Mohamed Abid (ARC, 2010)

Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation. - Imran Rafiq Quadri; Samy Meftali; Jean-Luc Dekeyser (DASIP, 2010)

Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis. - Sana Cherif; Imran Rafiq Quadri; Samy Meftali; Jean-Luc Dekeyser (DSD, 2010)

IP Based Configurable SIMD Massively Parallel SoC. - Mouna Baklouti; Mohamed Abid; Philippe Marquet; Jean-Luc Dekeyser (FPL, 2010)

Correct and energy-efficient design of SoCs: The H.264 encoder case study. - Adolf Samir Abdallah; Abdoulaye Gamatié; Jean-Luc Dekeyser (SoC, 2010)

A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantization. - Majdi Elhaji; Abdelkrim Zitouni; Samy Meftali; Jean-Luc Dekeyser; Rached Tourki (ISSPIT, 2010)

Traceability for Mutation Analysis in Model Transformation. - Vincent Aranega; Jean-Marie Mottu; Anne Etien; Jean-Luc Dekeyser (MoDELS (Workshops), 2010)

Parallel Sparse Matrix Solver on the GPU Applied to Simulation of Electrical Machines - Antonio Wendell De Oliveira Rodrigues; Frédéric Guyomarc'h; Yvonnick Le Menach; Jean-Luc Dekeyser (CoRR, 2010)

Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation. - Imran Rafiq Quadri; Huafeng Yu; Abdoulaye Gamatié; Éric Rutten; Samy Meftali; Jean-Luc Dekeyser (Int. J. Embed. Syst., 2010)

Scalable mpNoC for massively parallel systems - Design and implementation on FPGA. - Mouna Baklouti; Yassine Aydi; Philippe Marquet; Jean-Luc Dekeyser; Mohamed Abid (J. Syst. Archit., 2010)

Toward generic and adaptive avionic test systems. - George Afonso; Rabie Ben Atitallah; Nicolas Bélanger; Martial Rubio; Stephan Stilkerich; Jean-Luc Dekeyser (AHS, 2011)

High level design of adaptive distributed controller for partial dynamic reconfiguration in FPGA. - Sana Cherif; Chiraz Trabelsi; Samy Meftali; Jean-Luc Dekeyser (DASIP, 2011)

FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology. - Majdi Elhaji; Brahim Attia; Abdelkrim Zitouni; Rached Tourki; Samy Meftali; Jean-Luc Dekeyser (DASIP, 2011)

Fast and accurate hybrid power estimation methodology for embedded systems. - Santhosh Kumar Rethinagiri; Rabie Ben Atitallah; Smaïl Niar; Eric Senn; Jean-Luc Dekeyser (DASIP, 2011)

Hybrid system level power consumption estimation for FPGA-based MPSoC. - Santhosh Kumar Rethinagiri; Rabie Ben Atitallah; Smaïl Niar; Eric Senn; Jean-Luc Dekeyser (ICCD, 2011)

A system level power consumption estimation for MPSoC. - Santhosh Kumar Rethinagiri; Rabie Ben Atitallah; Jean-Luc Dekeyser (SoC, 2011)

A prototyping environment for high performance reconfigurable computing. - George Afonso; Rabie Ben Atitallah; Alexander Loyer; Jean-Luc Dekeyser; Nicolas Bélanger; Martial Rubio (ReCoSoC, 2011)

A model-driven based framework for rapid parallel SoC FPGA prototyping. - Mouna Baklouti; Manel Ammar; Philippe Marquet; Mohamed Abid; Jean-Luc Dekeyser (International Symposium on Rapid System Prototyping, 2011)

Programming Massively Parallel Architectures using MARTE: a Case Study - Antonio Wendell De Oliveira Rodrigues; Frédéric Guyomarc'h; Jean-Luc Dekeyser (CoRR, 2011)

A Modeling Approach based on UML/MARTE for GPU Architecture - Antonio Wendell De Oliveira Rodrigues; Frédéric Guyomarc'h; Jean-Luc Dekeyser (CoRR, 2011)

Automatic Multi-GPU Code Generation applied to Simulation of Electrical Machines - Antonio Wendell De Oliveira Rodrigues; Frédéric Guyomarc'h; Jean-Luc Dekeyser; Yvonnick Le Menach (CoRR, 2011)

Using an Alternative Trace for QVT. - Vincent Aranega; Anne Etien; Jean-Luc Dekeyser (Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2011)

A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design. - Chiraz Trabelsi; Rabie Ben Atitallah; Samy Meftali; Jean-Luc Dekeyser; Abderrazek Jemai (EURASIP J. Embed. Syst., 2011)

A multi-level design methodology of multistage interconnection network for MPSOCs. - Yassine Aydi; Mouna Baklouti; Mohamed Abid; Jean-Luc Dekeyser (Int. J. Comput. Appl. Technol., 2011)

A Model-Driven Design Framework for Massively Parallel Embedded Systems. - Abdoulaye Gamatié; Sébastien Le Beux; Éric Piel; Rabie Ben Atitallah; Anne Etien; Philippe Marquet; Jean-Luc Dekeyser (ACM Trans. Embed. Comput. Syst., 2011)

Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone. Vers l'exploration à haut niveau de l'architecture. - Adolf Samir Abdallah; Abdoulaye Gamatié; Jean-Luc Dekeyser (Tech. Sci. Informatiques, 2011)

Semi-distributed Control for FPGA-based Reconfigurable Systems. - Chiraz Trabelsi; Samy Meftali; Jean-Luc Dekeyser (DSD, 2012)

An efficient power estimation methodology for complex RISC processor-based platforms. - Santhosh Kumar Rethinagiri; Rabie Ben Atitallah; Jean-Luc Dekeyser; Eric Senn; Smaïl Niar (ACM Great Lakes Symposium on VLSI, 2012)

Broadcast with mask on a massively parallel processing on a chip. - Hana Krichene; Mouna Baklouti; Mohamed Abid; Philippe Marquet; Jean-Luc Dekeyser (HPCS, 2012)

Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study. - Gilberto Ochoa-Ruiz; Ouassila Labbani-Narsis; El-Bay Bourennane; Sana Cherif; Samy Meftali; Jean-Luc Dekeyser (ReConFig, 2012)

Dynamic reconfiguration of modular I/O IP cores for avionic applications. - Venkatasubramanian Viswanathan; Benjamin Nakache; Rabie Ben Atitallah; Maurice Nakache; Jean-Luc Dekeyser (ReConFig, 2012)

Distributed control for reconfigurable FPGA systems: A high-level design approach. - Chiraz Trabelsi; Samy Meftali; Jean-Luc Dekeyser (ReCoSoC, 2012)

Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems. - Pamela Wattebled; Jean-Philippe Diguet; Jean-Luc Dekeyser (ReCoSoC, 2012)

Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT. - Gilberto Ochoa-Ruiz; Ouassila Labbani; El-Bay Bourennane; Sana Cherif; Samy Meftali; Jean-Luc Dekeyser (RSP, 2012)

System level modeling methodology of NoC design from UML-MARTE to VHDL. - Majdi Elhaji; Pierre Boulet; Abdelkrim Zitouni; Samy Meftali; Jean-Luc Dekeyser; Rached Tourki (Des. Autom. Embed. Syst., 2012)

Abstract Clock-Based Design of a JPEG Encoder. - Adolf Samir Abdallah; Abdoulaye Gamatié; Rabie Ben Atitallah; Jean-Luc Dekeyser (IEEE Embed. Syst. Lett., 2012)

Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives. - Imran Rafiq Quadri; Abdoulaye Gamatié; Pierre Boulet; Samy Meftali; Jean-Luc Dekeyser (J. Syst. Archit., 2012)

A fast MPSoC virtual prototyping for intensive signal processing applications. - Rabie Ben Atitallah; Éric Piel; Smaïl Niar; Philippe Marquet; Jean-Luc Dekeyser (Microprocess. Microsystems, 2012)

Master-Slave Control Structure for Massively Parallel System on Chip. - Hana Krichene; Mouna Baklouti; Mohamed Abid; Philippe Marquet; Jean-Luc Dekeyser (DSD, 2013)

An MDE Approach for Automatic Code Generation from UML/MARTE to OpenCL. - Antonio Wendell De Oliveira Rodrigues; Frédéric Guyomarc'h; Jean-Luc Dekeyser (Comput. Sci. Eng., 2013)

A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme. - Majdi Elhaji; Abdelkrim Zitouni; Samy Meftali; Jean-Luc Dekeyser; Rached Tourki (Integr., 2013)

Decentralized control for dynamically reconfigurable FPGA systems. - Chiraz Trabelsi; Samy Meftali; Jean-Luc Dekeyser (Microprocess. Microsystems, 2013)

Model-driven design flow for distributed control in reconfigurable FPGA systems. - Chiraz Trabelsi; Samy Meftali; Rabie Ben Atitallah; Jean-Luc Dekeyser (DASIP, 2014)

Redefining the role of FPGAs in the next generation avionic systems (abstract only). - Venkatasubramanian Viswanathan; Rabie Ben Atitallah; Jean-Luc Dekeyser; Benjamin Nakache; Maurice Nakache (FPGA, 2014)

A generic pixel distribution architecture for parallel video processing. - Karim M. A. Ali; Rabie Ben Atitallah; Saïd Hanafi; Jean-Luc Dekeyser (ReConFig, 2014)

Communication-centric design for FMC based I/O system. - Mokhtar Bouain; Venkatasubramanian Viswanathan; Rabie Ben Atitallah; Jean-Luc Dekeyser (ReCoSoC, 2014)

Adaptivity in high-performance embedded systems: a reactive control model for reliable and flexible design. - Huafeng Yu; Abdoulaye Gamatié; Éric Rutten; Jean-Luc Dekeyser (Knowl. Eng. Rev., 2014)

Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System. - Venkatasubramanian Viswanathan; Rabie Ben Atitallah; Jean-Luc Dekeyser (FCCM, 2015)

A Parallel And Scalable Multi-FPGA based Architecture for High Performance Applications (Abstract Only). - Venkatasubramanian Viswanathan; Rabie Ben Atitallah; Jean-Luc Dekeyser; Benjamin Nakache; Maurice Nakache (FPGA, 2015)

Using hardware parallelism for reducing power consumption in video streaming applications. - Karim M. A. Ali; Rabie Ben Atitallah; Nizar Fakhfakh; Jean-Luc Dekeyser (ReCoSoC, 2015)

Adopting new learning strategies for computer architecture in higher education: case study: building the S3 microprocessor in 24 hours. - Jean-Luc Dekeyser; A. Shadi Aljendi (WCAE, 2015)

FPGA-based many-core System-on-Chip design. - Mouna Baklouti; Philippe Marquet; Jean-Luc Dekeyser; Mohamed Abid (Microprocess. Microsystems, 2015)

Towards an automation of the mutation analysis dedicated to model transformation. - Vincent Aranega; Jean-Marie Mottu; Anne Etien; Thomas Degueule; Benoit Baudry; Jean-Luc Dekeyser (Softw. Test. Verification Reliab., 2015)

AFFORDe: Automatic Allocation and Floorplanning for SPMD Architecture. - Wissem Chouchene; Rabie Ben Atitallah; Jean-Luc Dekeyser (MCSoC, 2016)

SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC. - Hana Krichene; Mouna Baklouti; Philippe Marquet; Jean-Luc Dekeyser; Mohamed Abid (PDP, 2016)

Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation. - Karim M. A. Ali; Rabie Ben Atitallah; Nizar Fakhfakh; Jean-Luc Dekeyser (ARC, 2017)

A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip. - Gilberto Ochoa-Ruiz; Pamela Wattebled; Maamar Touiza; Florent de Lamotte; El-Bay Bourennane; Samy Meftali; Jean-Luc Dekeyser; Jean-Philippe Diguet (J. Parallel Distributed Comput., 2018)

FPGA-Centric Design Process for Avionic Simulation and Test. - Rabie Ben Atitallah; Venkatasubramanian Viswanathan; Nicolas Bélanger; Jean-Luc Dekeyser (IEEE Trans. Aerosp. Electron. Syst., 2018)

ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures. - Karim M. A. Ali; Rabie Ben Atitallah; Abdessamad Ait El Cadi; Nizar Fakhfakh; Jean-Luc Dekeyser (Int. J. Reconfigurable Comput., 2019)

SCAC: Weakly-coupled execution model for massively parallel systems. - Hana Krichene; Mouna Baklouti; Philippe Marquet; Jean-Luc Dekeyser; Mohamed Abid (Microprocess. Microsystems, 2019)