A low-complexity video coder based on the Discrete Walsh Hadamard Transform. - Roberto Costantini; Javier Bracamonte; G. Ramponi; Jean-Luc Nagel; Michael Ansorge; Fausto Pellandini (EUSIPCO, 2000)

A low-power VLSI architecture for face verification using elastic graph matching. - Jean-Luc Nagel; Patrick Stadelmann; Michael Ansorge; Fausto Pellandini (EUSIPCO, 2002)

A multiscale morphological coprocessor for low-power face authentication. - Patrick Stadelmann; Jean-Luc Nagel; Michael Ansorge; Fausto Pellandini (EUSIPCO, 2002)

Optimized filterbank fingerprint recognition. - Erian Bezhani; Dequn Sun; Jean-Luc Nagel; Sergio Carrato (Image Processing: Algorithms and Systems, 2003)

Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures. - Christian Schuster; Jean-Luc Nagel; Christian Piguet; Pierre-André Farine (PATMOS, 2004)

An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth. - Christian Schuster; Christian Piguet; Jean-Luc Nagel; Pierre-André Farine (J. Low Power Electron., 2005)

Architectural and technology influence on the optimal total power consumption. - Christian Schuster; Jean-Luc Nagel; Christian Piguet; Pierre-André Farine (DATE, 2006)

Static and Dynamic Power Reduction by Architecture Selection. - Christian Piguet; Christian Schuster; Jean-Luc Nagel (PATMOS, 2006)

Low-power 32-bit dual-MAC 120 μW/MHz 1.0 V icyflex DSP/MCU core. - Claude Arm; Steve Gyger; Jean-Marc Masgonty; Marc Morgan; Jean-Luc Nagel; Christian Piguet; Flavio Rampogna; Patrick Volet (ESSCIRC, 2008)

Low-Power Heterogeneous Systems-on-Chips. - Christian Piguet; Jean-Luc Nagel; Vincent Peiris; Steve Gyger; Daniel Séverac; Marc-Nicolas Morgan; Jean-Marc Masgonty (J. Low Power Electron., 2008)

An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications. - Pierre-François Rüedi; Pascal Heim; Steve Gyger; François Kaess; Claude Arm; Ricardo Caseiro; Jean-Luc Nagel; Silvio Todeschini (ISSCC, 2009)

Low-Power 32-bit Dual-MAC 120 µW/MHz 1.0 V icyflex1 DSP/MCU Core. - Claude Arm; Steve Gyger; Jean-Marc Masgonty; Marc-Nicolas Morgan; Jean-Luc Nagel; Christian Piguet; Flavio Rampogna; Patrick Volet (IEEE J. Solid State Circuits, 2009)

A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits. - Luca Benini; Alberto Bocca; Alberto Bonanno; Alberto Macii; Enrico Macii; Jean-Luc Nagel; Christian Piguet; Massimo Poncino (J. Low Power Electron., 2010)

Energy parsimonious circuit design through probabilistic pruning. - Lingamneni Avinash; Christian C. Enz; Jean-Luc Nagel; Krishna V. Palem; Christian Piguet (DATE, 2011)

Maximum delay variation temperature-aware standard cell design. - Marc Pons 001; Jean-Luc Nagel; Christian Piguet (ICECS, 2012)

Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation. - Marc Pons 001; Jean-Luc Nagel; Daniel Séverac; Marc-Nicolas Morgan; Daniel Sigg; Pierre-François Rüedi; Christian Piguet (PATMOS, 2013)

Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation. - Marc Pons 001; Thanh-Chau Le; Claude Arm; Daniel Séverac; Jean-Luc Nagel; Marc-Nicolas Morgan; Stéphane Emery (ESSCIRC, 2016)

Ultra low power microelectronics for wearable and medical devices. - Pierre-François Rüedi; A. Bishof; Marcin K. Augustyniak; Pascal Persechini; Jean-Luc Nagel; Marc Pons 001; Stéphane Emery; Olivier Chételat (DATE, 2017)

A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS. - Marc Pons 001; Christoph Thomas Müller; David Ruffieux; Jean-Luc Nagel; Stéphane Emery; Andreas Burg 001; Shuuji Tanahashi; Yoshitaka Tanaka; Atsushi Takeuchi (CICC, 2019)

Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW. - Jian Deng; Jean-Luc Nagel; Loïc Zahnd; Marc Pons 001; David Ruffieux; Claude Arm; Pascal Persechini; Stéphane Emery (ISLPED, 2019)

Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC. - Christoph Thomas Müller; Marc Pons 001; David Ruffieux; Jean-Luc Nagel; Stéphane Emery; Andreas Burg 001; Shuuji Tanahashi; Yoshitaka Tanaka; Atsushi Takeuchi (PRIME, 2019)

Multi-Electroanalytical Method Capable, Duty-Cycled, 0.36 mm2 Electrochemical Frontend, Achieving 170dB Current Sensing Range with Extended Compliance Voltage Adopting Feedforward Cancellation. - Amrith Sukumaran; Francesco Caruso; Régis Cattenoz; B. Putter; Jean-Luc Nagel; R. Ravanilla; I. Stergiou; G. Bouilly; P. Nussbaum; Stéphane Emery (CICC, 2025)