Synthesis of system-level communication by an allocation-based approach. - Jean-Marc Daveau; Tarek Ben Ismail; Ahmed Amine Jerraya (ISSS, 1995)

A system-level communication synthesis approach for hardware/software systems. - Tarek Ben Ismail; Jean-Marc Daveau; Kevin O'Brien; Ahmed Amine Jerraya (Microprocess. Microsystems, 1996)

Transformational partitioning for co-design of multiprocessor systems. - Gilberto Fernandes Marchioro; Jean-Marc Daveau; Ahmed Amine Jerraya (ICCAD, 1997)

Protocol selection and interface generation for HW-SW codesign. - Jean-Marc Daveau; Gilberto Fernandes Marchioro; Tarek Ben Ismail; Ahmed Amine Jerraya (IEEE Trans. Very Large Scale Integr. Syst., 1997)

Hardware/software co-design of an ATM network interface card: a case study. - Jean-Marc Daveau; Gilberto Fernandes Marchioro; Ahmed Amine Jerraya (CODES, 1998)

Hardware/Software Co-Design Methodology for Design of Embedded Systems. - Mohamed Abid; Tarek Ben Ismail; Adel Changuel; Carlos A. Valderrama; Mohamed Romdhani; Gilberto Fernandes Marchioro; Jean-Marc Daveau; Ahmed Amine Jerraya (Integr. Comput. Aided Eng., 1998)

Communication Interface Synthesis for Multilanguage Specifications. - Fabiano Hessel; Philippe Coste; P. LeMarrec; Nacer-Eddine Zergainoh; Jean-Marc Daveau; Ahmed Amine Jerraya (IEEE International Workshop on Rapid System Prototyping, 1999)

Interlanguage Communication Synthesis for Heterogeneous Specifications. - Fabiano Hessel; Pascal Coste; Philippe Le Marrec; Nacer-Eddine Zergainoh; Gabriela Nicolescu; Jean-Marc Daveau; Ahmed Amine Jerraya (Des. Autom. Embed. Syst., 2000)

Automating the Design of SOCs Using Cores. - Reinaldo A. Bergamaschi; Subhrajit Bhattacharya; Ronoldo Wagner; Colleen Fellenz; Michael Muhlada; William R. Lee; Foster White; Jean-Marc Daveau (IEEE Des. Test Comput., 2001)

FlexCC2: An Optimizing Retargetable C Compiler for DSP Processors. - Valérie Bertin; Jean-Marc Daveau; Philippe Guillaume; Thierry Lepley; Denis Pilat; Claire Richard; Miguel Santana; Thomas Thery (EMSOFT, 2002)

A retargetable register allocation framework for embedded processors. - Jean-Marc Daveau; Thomas Thery; Thierry Lepley; Miguel Santana (LCTES, 2004)

Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS. - Philippe Roche; Mark Lysinger; Gilles Gasiot; Jean-Marc Daveau; Mehdi Zamanian; Pierre Dautriche (IOLTS, 2008)

Verification of soft error detection mechanism through fault injection on hardware emulation platform. - Oscar Bailan; Umberto Rossi; Anne Wantens; Jean-Marc Daveau; Salvatore Nappi; Philippe Roche (DSN Workshops, 2010)

Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimation. - Josep Torras Flaquer; Jean-Marc Daveau; Lirida A. B. Naviner; Philippe Roche (ICECS, 2010)

Fast reliability analysis of combinatorial logic circuits using conditional probabilities. - Josep Torras Flaquer; Jean-Marc Daveau; Lirida A. B. Naviner; Philippe Roche (Microelectron. Reliab., 2010)

An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. - Josep Torras Flaquer; Jean-Marc Daveau; Lirida A. B. Naviner; Philippe Roche (IOLTS, 2011)

28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors. - Fady Abouzeid; Sylvain Clerc; Cyril Bottoni; Benjamin Coeffic; Jean-Marc Daveau; Damien Croain; Gilles Gasiot; Dimitri Soussan; Philippe Roche (ESSCIRC, 2015)

Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test. - Cyril Bottoni; Benjamin Coeffic; Jean-Marc Daveau; Gilles Gasiot; Fady Abouzeid; Sylvain Clerc; Lirida A. B. Naviner; Philippe Roche (IRPS, 2015)

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. - Sylvain Clerc; Fady Abouzeid; Darayus Adil Patel; Jean-Marc Daveau; Cyril Bottoni; Lorenzo Ciampolini; Fabien Giner; David Meyer; Robin Wilson; Philippe Roche; Sylvie Naudet; Arnaud Virazel; et al. (ISQED, 2015)

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. - Sylvain Clerc; Mehdi Saligane; Fady Abouzeid; Martin Cochet; Jean-Marc Daveau; Cyril Bottoni; David Bol; Julien De Vos; Dominique Zamora; Benjamin Coeffic; Dimitri Soussan; Damien Croain; et al. (ISSCC, 2015)

Partial triplication of a SPARC-V8 microprocessor using fault injection. - Cyril Bottoni; Benjamin Coeffic; Jean-Marc Daveau; Lirida A. B. Naviner; Philippe Roche (LASCAS, 2015)

30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation. - Fady Abouzeid; Christophe Bernicot; Sylvain Clerc; Jean-Marc Daveau; Gilles Gasiot; Daniel Noblet; Dimitri Soussan; Philippe Roche (ESSCIRC, 2016)

A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI. - Guenole Lallement; Fady Abouzeid; Martin Cochet; Jean-Marc Daveau; Philippe Roche; Jean-Luc Autran (ESSCIRC, 2017)

A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI. - Guenole Lallement; Fady Abouzeid; Martin Cochet; Jean-Marc Daveau; Philippe Roche; Jean-Luc Autran (IEEE J. Solid State Circuits, 2018)

FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip. - Sébastien Thomet; Serge De Paoli; Jean-Marc Daveau; Valérie Bertin; Fady Abouzeid; Philippe Roche; Fakhreddine Ghaffari; Olivier Romain (DFT, 2021)

Automated Dysfunctional Model Extraction for Model Based Safety Assessment of Digital Systems. - Tiziano Fiorucci; Jean-Marc Daveau; Giorgio Di Natale; Philippe Roche (IOLTS, 2021)

Software Product Reliability Based on Basic Block Metrics Recomposition. - Tiziano Fiorucci; Giorgio Di Natale; Jean-Marc Daveau; Philippe Roche (IOLTS, 2022)

Formal Temporal Characterization of Register Vulnerability in Digital Circuits. - Damiano Zuccalà; Jean-Marc Daveau; Philippe Roche; Katell Morin-Allory (ISVLSI, 2023)

Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning. - Esther Goudet; Luis Peña Treviño; Lirida A. B. Naviner; Jean-Marc Daveau; Philippe Roche (LATS, 2023)

Formal Resilience Metric Characterization in Complex Digital Systems. - Damiano Zuccalà; Jean-Marc Daveau; Philippe Roche; Katell Morin-Allory (ETS, 2024)

Formal Fault Injection in Digital Blocks with Mined Assertions. - Damiano Zuccalà; Paul Breuil; Jean-Marc Daveau; Philippe Roche; Katell Morin-Allory (MEMOCODE, 2024)

Drift of Combinational Circuits Failure Rates with a Probabilistic Model Approximated by Partitioning. - Esther Goudet; Luis Peña Treviño; Gutemberg G. dos Santos Júnior; Sayah El Hajji; Fabio Sureau; Lirida Naviner; Jean-Marc Daveau; Philippe Roche (SBCCI, 2024)

Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach. - Esther Goudet; Fabio Sureau; Paul Breuil; Luis Peña Treviño; Lirida A. B. Naviner; Jean-Marc Daveau; Philippe Roche (J. Electron. Test., 2024)

Comparative Study of Safety and Security-Protected AES Designs. - Daniel Thirion; Jean-Marc Daveau; Valentin Egloff; David Hély; Vincent Beroulle; Philippe Roche (DDECS, 2025)

Approximate Analytical Model Evaluating Digital Systems Compliance with Automotive Standards. - Esther Goudet; Fabio Sureau; Manan Kaila; Rémi Germe; Luis Peña Treviño; Jean-Marc Daveau; Lirida Naviner; Philippe Roche (LATS, 2025)