Boolean and current detection of MOS transistor with gate oxide short. - Michel Renovell; Jean Marc Gallière; Florence Azaïs; Serge Bernard; Yves Bertrand (ITC, 2001)

Electrical Analysis of Gate Oxide Short in MOS Technologies. - Michel Renovell; Jean Marc Gallière; Florence Azaïs; Yves Bertrand (LATW, 2001)

Modeling gate oxide short defects in CMOS minimum transistors. - Michel Renovell; Jean Marc Gallière; Florence Azaïs; Yves Bertrand (ETW, 2002)

Delay Testing of MOS Transistor with Gate Oxide Short. - Michel Renovell; Jean Marc Gallière; Florence Azaïs; Yves Bertrand (Asian Test Symposium, 2003)

Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. - Michel Renovell; Jean Marc Gallière; Florence Azaïs; Yves Bertrand (J. Electron. Test., 2003)

Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. - Ilia Polian; Sandip Kundu; Jean-Marc Gallière; Piet Engelke; Michel Renovell; Bernd Becker 001 (VTS, 2005)

Delay Testing Viability of Gate Oxide Short Defects. - Jean Marc Gallière; Michel Renovell; Florence Azaïs; Yves Bertrand (J. Comput. Sci. Technol., 2005)

Stream Manager, Easy CAD Tools Switching in Academic Context. - Jean-Marc Gallière; Guy Cathébras (MSE, 2007)

A 2-D VHDL-AMS Model for Disk-Shape Piezoelectric Transducers. - Jean-Marc Gallière; Philippe Papet; Laurent Latorre (BMAS, 2008)

A mixed TCAD/Electrical simulation laboratory to open up the microelectronics teaching. - Jean-Marc Gallière; Jerome Boch (MSE, 2009)

A roaming memory test bench for detecting particle induced SEUs. - Jean-Marc Gallière; Paolo Rech; Patrick Girard 001; Luigi Dilillo (ITC, 2010)

Neutron detection in atmospheric environment through static and dynamic SRAM-based test bench. - Luigi Dilillo; Paolo Rech; Jean-Marc Gallière; Patrick Girard 001; Frederic Wrobel; Frédéric Saigné (LATW, 2011)

Versatile march test generator for hands-on memory testing laboratory. - Jean-Marc Gallière; Luigi Dilillo (MSE, 2011)

A toolkit to demystify CMOS Active Pixel Sensors. - Jean-Marc Gallière; Jerome Boch (MSE, 2013)

Testing for gate oxide short defects using the detectability interval paradigm. - Jean-Marc Gallière; Florence Azaïs; Mariane Comte; Michel Renovell (it Inf. Technol., 2014)

Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations. - Amit Karel; Mariane Comte; Jean-Marc Gallière; Florence Azaïs; Michel Renovell (ISVLSI, 2016)

Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect. - Amit Karel; Mariane Comte; Jean-Marc Gallière; Florence Azaïs; Michel Renovell (LATS, 2016)

Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions. - Amit Karel; Florence Azaïs; Mariane Comte; Jean-Marc Gallière; Michel Renovell; Keshav Singh (ETS, 2017)

Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology. - Amit Karel; Florence Azaïs; Mariane Comte; Jean-Marc Gallière; Michel Renovell; Keshav Singh (ISVLSI, 2017)

Analysis of short defects in FinFET based logic cells. - Freddy Forero; Jean-Marc Gallière; Michel Renovell; Víctor H. Champac (LATS, 2017)

Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies. - Amit Karel; Mariane Comte; Jean-Marc Gallière; Florence Azaïs; Michel Renovell (J. Electron. Test., 2017)

Thermal Scans for Detecting Hardware Trojans. - Maxime Cozzi; Jean-Marc Gallière; Philippe Maurine (COSADE, 2018)

Exploiting Phase Information in Thermal Scans for Stealthy Trojan Detection. - Maxime Cozzi; Jean-Marc Gallière; Philippe Maurine (DSD, 2018)

Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies. - Amit Karel; Florence Azaïs; Mariane Comte; Jean-Marc Gallière; Michel Renovell (LATS, 2018)

Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management. - Rida Kheirallah; Jean-Marc Gallière; Nadine Azémard; Gilles R. Ducharme (PATMOS, 2018)

Detectability Challenges of Bridge Defects in FinFET Based Logic Cells. - Freddy Forero; Jean-Marc Gallière; Michel Renovell; Víctor H. Champac (J. Electron. Test., 2018)

A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells. - Freddy Forero; Jean-Marc Gallière; Michel Renovell; Víctor H. Champac (LATS, 2019)

Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies. - Amit Karel; Florence Azaïs; Mariane Comte; Jean-Marc Gallière; Michel Renovell (J. Electron. Test., 2019)

A Simple Protocol to Compare EMFI Platforms. - Julien Toulemont; N. Ouldei-Tebina; Jean Marc Gallière; Pascal Nouet; E. Bourbao; Philippe Maurine (IACR Cryptol. ePrint Arch., 2020)

Iterative Method for Performance Prediction Improvement of Integrated Circuits. - Gwenael Chaillou; Philippe Maurine; Jean-Marc Gallière; Nadine Azémard (DCIS, 2021)

On the scaling of EMFI probes. - Julien Toulemont; Geoffrey Chancel; Jean Marc Gallière; Frédérick Mailly; Pascal Nouet; Philippe Maurine (FDTC, 2021)

Body Biasing Injection: To Thin or Not to Thin the Substrate? - Geoffrey Chancel; Jean Marc Gallière; Philippe Maurine (COSADE, 2022)

Body Biasing Injection: Impact of substrate types on the induced disturbancesƒ. - Geoffrey Chancel; Jean Marc Gallière; Philippe Maurine (FDTC, 2022)

A better practice for Body Biasing Injection. - Geoffrey Chancel; Jean-Marc Gallière; Philippe Maurine (FDTC, 2023)

Cost-Effective Analytical Models of Resistive Opens Defects in FinFET Technology. - Gustavo Aguirre; Freddy Forero; Víctor H. Champac; Michel Renovell; Florence Azaïs; Mariane Comte; Jean-Marc Gallière (IEEE Trans. Very Large Scale Integr. Syst., 2025)