A low-power and high-speed quaternary interconnection link using efficient converters. - Jean-Marc Philippe; Sébastien Pillement; Olivier Sentieys (ISCAS (5), 2005)

An energy-efficient ternary interconnection link for asynchronous systems. - Jean-Marc Philippe; E. Kinvi-Boh; Sébastien Pillement; Olivier Sentieys (ISCAS, 2006)

Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects. - Jean-Marc Philippe; Sébastien Pillement; Olivier Sentieys (ISQED, 2006)

On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project. - Katarina Paulsson; Michael Hübner 001; Jürgen Becker 001; Jean-Marc Philippe; Christian Gamrat (FPL, 2007)

Self-Adaptive Networked Entities for Building Pervasive Computing Architectures. - Martin Danek; Jean-Marc Philippe; Petr Honzík; Christian Gamrat; Roman Bartosinski (ICES, 2008)

An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency. - Chris R. Jesshope; Jean-Marc Philippe; Michiel W. van Tol (SAMOS, 2008)

A Self-reconfigurable FPGA-Based Platform for Prototyping Future Pervasive Systems. - Jean-Marc Philippe; Benoît Tain; Christian Gamrat (ICES, 2010)

Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect. - Sébastien Pillement; Olivier Sentieys; Jean-Marc Philippe (Microelectron. J., 2010)

An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture. - Farhat Thabet; Yves Lhuillier; Caaliph Andriamisaina; Jean-Marc Philippe; Raphaël David (DATE, 2013)

Parallel Architecture Benchmarking: From Embedded Computing to HPC, a FiPS Project Perspective. - Yves Lhuillier; Jean-Marc Philippe; Alexandre Guerre; Michal Kierzynka; Ariel Oleksiak (EUC, 2014)

HARS: A hardware-assisted runtime software for embedded many-core architectures. - Yves Lhuillier; Maroun Ojail; Alexandre Guerre; Jean-Marc Philippe; Karim Ben Chehida; Farhat Thabet; Caaliph Andriamisaina; Chafic Jaber; Raphaël David (ACM Trans. Embed. Comput. Syst., 2014)

Exploration and design of embedded systems including neural algorithms. - Jean-Marc Philippe; Alexandre Carbon; Olivier Brousse; Michel Paindavoine (DATE, 2015)

NeuroDSP Accelerator for Face Detection Application. - Michel Paindavoine; Olivier Boisard; Alexandre Carbon; Jean-Marc Philippe; Olivier Brousse (ACM Great Lakes Symposium on VLSI, 2015)

The M2DC Project: Modular Microserver DataCentre. - Mariano Cecowski; Giovanni Agosta; Ariel Oleksiak; Michal Kierzynka; Micha vor dem Berge; Wolfgang Christmann; Stefan Krupop; Mario Porrmann; Jens Hagemeyer; René Griessl; Meysam Peykanu; Lennart Tigges; et al. (DSD, 2016)

Data centres for IoT applications: The M2DC approach (Invited paper). - Michal Kierzynka; Ariel Oleksiak; Giovanni Agosta; Carlo Brandolese; William Fornaciari; Gerardo Pelosi; Micha vor dem Berge; Wolfgang Christmann; Stefan Krupop; Mariano Cecowski; Robert Plestenjak; Justin Cinkelj; et al. (SAMOS, 2016)

Modeling of Applications and Hardware to Explore Task Mapping and Scheduling Strategies on a Heterogeneous Micro-Server System. - Lilia Zaourar; Massinissa Ait Aba; David Briand; Jean-Marc Philippe (IPDPS Workshops, 2017)

M2DC - Modular Microserver DataCentre with heterogeneous hardware. - Ariel Oleksiak; Michal Kierzynka; Wojciech Piatek; Giovanni Agosta; Alessandro Barenghi; Carlo Brandolese; William Fornaciari; Gerardo Pelosi; Mariano Cecowski; Robert Plestenjak; Justin Cinkelj; Mario Porrmann; et al. (Microprocess. Microsystems, 2017)

PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks. - Alexandre Carbon; Jean-Marc Philippe; Olivier Bichler; Renaud Schmit; Benoît Tain; David Briand; Nicolas Ventroux; Michel Paindavoine; Olivier Brousse (DATE, 2018)

Task management on fully heterogeneous micro-server system: Modeling and resolution strategies. - Lilia Zaourar; Massinissa Ait Aba; David Briand; Jean-Marc Philippe (Concurr. Comput. Pract. Exp., 2018)

Deep Neural Networks Characterization Framework for Efficient Implementation on Embedded Systems. - Nermine Ali; Jean-Marc Philippe; Benoît Tain; Thomas Peyret; Philippe Coussy (SiPS, 2020)

SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency. - Ivan Miro Panades; Benoît Tain; Jean-Frédéric Christmann; David Coriat; Romain Lemaire; Clement Jany; Baudouin Martineau; Fabrice Chaix; Anthony Quelen; Emmanuel Pluchart; Jean-Philippe Noel; Reda Boumchedda; et al. (VLSI Circuits, 2020)

Analysis of on-chip communication properties in accelerator architectures for deep neural networks. - Hana Krichene; Jean-Marc Philippe (NOCS, 2021)

Exploration and Generation of Efficient FPGA-based Deep Neural Network Accelerators. - Nermine Ali; Jean-Marc Philippe; Benoît Tain; Philippe Coussy (SiPS, 2021)

Generating Efficient FPGA-based CNN Accelerators from High-Level Descriptions. - Nermine Ali; Jean-Marc Philippe; Benoît Tain; Philippe Coussy (J. Signal Process. Syst., 2022)

eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem. - Lluc Alvarez; Abraham Ruiz; Arnau Bigas-Soldevilla; Pavel Kuroedov; Alberto González 004; Hamsika Mahale; Noe Bustamante; Albert Aguilera; Francesco Minervini; Javier Salamero; Oscar Palomar; Vassilis Papaefstathiou; et al. (CF, 2023)

A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors. - Lilia Zaourar; Alice Chillet; Jean-Marc Philippe (DSD, 2023)

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration. - Ivan Miro-Panades; Benoît Tain; Jean-Frédéric Christmann; David Coriat; Romain Lemaire; Clement Jany; Baudouin Martineau; Fabrice Chaix; Guillaume Waltener; Emmanuel Pluchart; Jean-Philippe Noel; Adam Makosiej; et al. (IEEE J. Solid State Circuits, 2023)