A design approach for networks of Self-Sampled All-Digital Phase-Locked Loops. - Jean-Michel Akre; Jérôme Juillard; Mohammad Javidan; Eldar Zianbetov; Dimitri Galayko; Anton Korniienko; Éric Colinet (ECCTD, 2011)

All-digital PLL array provides reliable distributed clock for SOCs. - Mohammad Javidan; Eldar Zianbetov; François Anceau; Dimitri Galayko; Anton Korniienko; Éric Colinet; Gérard Scorletti; Jean-Michel Akre; Jérôme Juillard (ISCAS, 2011)

Synchronization Analysis of Networks of Self-Sampled All-Digital Phase-Locked Loops. - Jean-Michel Akre; Jérôme Juillard; Dimitri Galayko; Éric Colinet (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)