Delay modelling improvement for low voltage applications. - Jean Michel Daga; Michel Robert; Daniel Auvergne (EURO-DAC, 1995)

Internal power modelling and minimization in CMOS inverters. - S. Turgis; Jean Michel Daga; Josep M. Portal; Daniel Auvergne (ED&TC, 1997)

Temperature Effect on Delay for Low Voltage Applications. - Jean Michel Daga; E. Ottaviano; Daniel Auvergne (DATE, 1998)

A comprehensive delay macro modeling for submicrometer CMOS logics. - Jean Michel Daga; Daniel Auvergne (IEEE J. Solid State Circuits, 1999)

Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions. - Jean Michel Daga; Caroline Papaix; Marc Merandat; Stephane Ricard; Giuseppe Medulla; Jeanine Guichaoua; Daniel Auvergne (MTDT, 2000)

Test and Repair of Embedded Flash Memories. - Jean Michel Daga (ITC, 2002)

A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile Memories. - Caroline Papaix; Jean Michel Daga (MTDT, 2002)

A 40ns Random Access Time Low Voltage 2Mbits EEPROM Memory for Embedded Applications. - Jean Michel Daga; Caroline Papaix; Emmanuel Racape; Marylene Combe; Vincent Sialelli; Jeanine Guichaoua (MTDT, 2003)

Design Techniques for EEPROMs Embedded in Portable Systems on Chips. - Jean Michel Daga; Caroline Papaix; Marc Merandat; Stephane Ricard; Giuseppe Medulla; Jeanine Guichaoua; Daniel Auvergne (IEEE Des. Test Comput., 2003)

Embedded EEPROM Speed Optimization Using System Power Supply Resources. - Jean Michel Daga; Caroline Papaix; Marylene Combe; Emmanuel Racape; Vincent Sialelli (PATMOS, 2004)

A PMOS-switch based charge pump, allowing lost cost implementation on a CMOS standard process. - Emmanuel Racape; Jean Michel Daga (ESSCIRC, 2005)

An Overview of Failure Mechanisms in Embedded Flash Memories. - Olivier Ginez; Jean Michel Daga; Marylene Combe; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (VTS, 2006)

Evaluation of design for reliability techniques in embedded flash memories. - Benoît Godard; Jean Michel Daga; Lionel Torres; Gilles Sassatelli (DATE, 2007)

Architecture for Highly Reliable Embedded Flash Memories. - Benoît Godard; Jean Michel Daga; Lionel Torres; Gilles Sassatelli (DDECS, 2007)

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. - Olivier Ginez; Jean Michel Daga; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (ETS, 2007)

A concurrent approach for testing address decoder faults in eFlash memories. - Olivier Ginez; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Jean Michel Daga (ITC, 2007)

Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. - Olivier Ginez; Jean Michel Daga; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (VTS, 2007)

Hierarchical Code Correction and Reliability Management in Embedded nor Flash Memories. - Benoît Godard; Jean Michel Daga; Lionel Torres; Gilles Sassatelli (ETS, 2008)

A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. - Olivier Ginez; Jean Michel Daga; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 2009)

A statistical design method for Giga Bit memory arrays and beyond. - Christian Caillat; Eric Carman; Jean Michel Daga; Cedric Ouvrard; Philippe Bauser (ICECS, 2010)